STPM11_08 STMICROELECTRONICS [STMicroelectronics], STPM11_08 Datasheet - Page 30

• Manufacturer Part Number: STPM11_08
• Description: Single phase energy metering IC with pulsed output and digital calibration
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 15.
7.17
30/45
Signal
PUMP
Name
WE
RD
Value
The mode signals bit can be written using the normal writing procedure of the CFGI
interface (see CFGI par. 7.17)
Mode signals description
CFGI: Configuration interface
The CFGI interface supports a simple serial protocol, which is implemented in order to
enable the configuration of STPM1x which allows writing the Mode bits and the
configuration bits (temporarily or permanently);
Four pins of the device are dedicated to this purpose: SCS, SYN-NP, SCLNCN, SDATD.
SCS, SYN-NP, SCL-NLC and SDATD are all input pins. A high level signal for these pins
means a voltage level higher than 0.75xV
lower than 0.25xV
The condition in which SCS, SYN-NP and SCL-NLC inputs are set to high level determines
the idle state of the CFGI interface and no data transfer occurs.
Bit
0
1
0
1
0
1
– RD mode signal has been already described in par. 7.15 (configuring the STPM1x),
– PUMP. When set, the PUMP mode signal transforms the MOP and MON pins to act
– WE (write Enable): This mode signal is used to permanently write to the OTP anti-
– SCS: in the STPM1X, the SYN-NP, SCL-NLC and SDA-TD have the dual task to
but there is another implied function of the signal RD. When it is set, each sense
amplifier is disconnected from corresponding anti-fuse element and this way, its 3V
NMOS gate is protected from the high voltage of V
operation. This means that as long as the V
signal RD should be set.
as driving signals to implement a charge-pump DC-DC converter (see
This feature is useful in order to boost the V
generate the V
elements.
fuse element. When this bit is not set, any writing to the configuration bit is recorded
in the shadow latches. When this bit is set, the writing is recorded both in the shadow
latch and in the OTP anti-fuse element.
provide information on the meter status (see Pin Description table) and to allow CFGI
communication. The SCS pin allows using the above pins for CFGI communication
when it is low and allows the normal operation of SYN-NP, SCL-NLC and SDA-TD
MOP and MON operate normally
MOP and MON provide the driving signals to implement a
charge-pump DC-DC converter
The 56 Configuration bits originated by OTP anti-fuses
The 56 Configuration bits originated by shadow latches
Any writing in the configuration bits is recorded in the shadow
latches
Any writing in the configuration bits is recorded both in the
shadow latches and in the OTP anti-fuse elements
CC
.
OTP
voltage (14 V to 20 V) needed to program the OTP anti-fuse
Status
CC
, while a low level signal means a voltage value
OTP
CC
supply voltage of the STPM1x to
voltage reads more than 3V, the
OTP
during permanent write
Command
0111000x
1111000x
0111101x
1111101x
0111110x
1111110x
Binary
Figure
Command
FC or FD
FA or FB
7C or 7D
F0 or F1
7A or 7B
70 or 71
Hex
23).