A6850 ALTERA [Altera Corporation], A6850 Datasheet - Page 11

• Manufacturer Part Number: A6850
• Description: Asynchronous Communications Interface Adapter
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
Figure 4. a6850 Receiver Functional Waveforms
Sampling Pulse
Divide-by-1 Mode
Divide-by-16 Mode
or txclk
Sampled on rising edge of rxclk
Driven from falling edge of txclk
rxdata
txdata
rxdata
txdata
rxclk
rxclk
txclk
Data Bit Sampling
After detecting a logic low, the a6850 samples and shifts the data into the
input shift register. Data bit sampling occurs on every rising edge in
divide-by-1 mode, every 16 rising edges in divide-by-16 mode, and every
64 rising edges in divide-by-64 mode. Each time a bit is sampled, parity is
calculated for future error detection. See
Parity & Stop Bit Detection
The a6850 counts the number of data bits as it shifts. When the number of
data bits received matches the number specified in the control register, the
a6850 expects either a parity bit or a stop bit.
If parity is enabled, the a6850 samples for the parity bit, which is then
processed for parity. However, if parity is not enabled, the a6850 samples
for a stop bit (i.e., logic high). If a logic low is sampled, the fe bit is set in
the status register.
a6850 Asynchronous Communications Interface Adapter Data Sheet
Start Bit
Start Bit
Figure
4.
Data Bit
Data Bit
91