MC44S803EP FREESCALE [Freescale Semiconductor, Inc], MC44S803EP Datasheet - Page 8

• Manufacturer Part Number: MC44S803EP
• Description: Low Power CMOS Broadband Tuner
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

with Serial Peripheral Interface (SPI) or I
are shared between the two buses. A Bus Select pin,
(BusSel), as shown in Table 8, is used to determine which
bus will be used. The BUSSEL pin has an internal pull-up
resistor. For a logic one the pin may be left open and for a
logic zero it should be connected to ground.
addresses. This allows up to four tuners on the same bus for
applications that use multiple tuners. The two pins used for
the I
bi-directional. The SPI bus uses four pins: Slave Select (SS),
Serial Clock (SCLK), Master Out Slave In (MOSI), and
Master In Slave Out (MISO). Data is read from the part
through the MISO pin. For multiple tuner application using the
SPI interface, each device shares the Clock, MOSI and MISO
lines. Each device is supplied its own Slave Select line. The
Slave Select and MISO pins for the SPI share the same pins
as the two address lines for the I
buses share the same Control, Data, and Shift registers that
interface with each section of the IC.
Table 8. Interface Bus Selection
SERIAL PERIPHERAL INTERFACE (SPI) OPERATION
device. The input data stream is clocked on the rising edge of
SCLK into a shift register with the MSB first. If more than
24 bits are clocked in only the last 24 bits inputted are
MC44S803
8
The digital control interface has the capability to interface
For the I
A 24-bit shift register is used to shift data in and out of the
Bus Select Pin
2
C bus are the Clock and Data pins. The data pin is
0
1
2
C bus, two pins are used to select one of four I
2
Interface Standard
C bus. Internally, the two
SPI
I
2
2
C buses. Five pins
C
DIGITAL INTERFACE
2
C
recognized. If less than 24 bits are required, only the required
bits need to be clocked in. No back filling is required. The
output data stream is clocked out of the shift register on the
falling edge of SCLK with the MSB first. The bus master
samples the MISO line on the rising edge of SCLK. Every SPI
operation is both a read and a write operation, since the data
is input on one pin and output on a different pin. Read data
out while clocking data in. The data stored in the shift register
is loaded into one of the appropriate registers after the rising
edge of SS. The 4 LSBs are the Control Register Address
Bits.
I
out of the part. The input data stream is clocked in on the
rising edge of SCLK into the shift register with the MSB first.
The IC Address and R/W bit are sent first. This allows the IC
to determine if it is the device that is being communicated
with. After that, 24 bits are clocked in to control the IC. If less
than 24 bits are required, then 16 or 8 bits could be used. In
other words, commands can be sent in 1, 2, or 3 byte
increments depending on the requirements for the particular
control register you are writing to. Data can be read back from
the IC in 1, 2, or 3 byte increments also. The Master controls
the clock line, whether writing to the part or reading from it.
After each byte that is sent, the device that receives it sends
an acknowledge bit. The output data stream is clocked out of
the shift register on the falling edge of SCLK and valid on the
rising edge, with the MSB first. The data stored in the shift
register is loaded into one of the appropriate registers after
the Stop Condition is sent. The 4 LSBs are the Control
Register Address Bits.
2
C OPERATION
The same 24-bit shift register is used to shift data in and
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