MC44145D MOTOROLA [Motorola, Inc], MC44145D Datasheet - Page 4

• Manufacturer Part Number: MC44145D
• Description: PIXEL CLOCK GENERATOR / SYNC SEPARATOR
• Manufacturer: MOTOROLA [Motorola, Inc]

Composite Sync Separator
two blocks, a sync slicer and a sync amplifier, which can be
used to extract the vertical sync and composite sync
information from a video signal.
video signal is slightly integrated and then sliced at a ratio of
4.7 to 64 which corresponds to the sync to horizontal ratio.
Two outputs are given, one of high impedance and the other
low impedance.
one output to be used for composite sync and the other
output to be integrated and then sliced using the slicing
amplifier to extract the vertical sync information.
Clock Generation
emitter–coupled VCO followed by a switchable 2 to provide
a 50% duty cycle wherever required, or twice the set
frequency if an external divider is used. The clock generator
is a PLL subsection; its function is the generation of a high
NOTE: The two V CC pins are not independent, as they are internally connected by means of the input protection diodes; they must always be both connected
4
The composite sync separation section is comprised of
The sync separator is an adaptive slicer in which the
A slicing sync inverting amplifier is also on–chip, allowing
The clock generation is made up of a wide ranging
Pin
10
12
13
14
11
1
2
3
4
5
6
7
8
9
to a suitable V CC line.
NPD Gain
Ground
Sync B
Sync Amp In
Sync C
V CC
Clock Out
Div 2 EN
F ref
Sync Amp Out
V CC2
Video In
NBACK
PLL Loop Filter
Function
This pin sets the gain of the phase frequency detector by changing the current of the charge pump
output (40 A or 80 A). Low current with this pin
Ground connection common to the PLL and sync separator sections.
High impedance sync output.
Sync amplifier input.
Low impedance sync output.
Power connection to the PLL section.
VCO clock output. Capable of limited LSTTL drive. It should not be used to drive high capacitive
loads, such as long PCB traces or coaxial lines.
The divider is switched in with this pin
Reference frequency input to the phase and frequency comparator. Typically this will be a 15625
(15750) Hz signal. It is rising edge sensitive. Due to the nature of the phase and frequency
comparator, no missing pulses are tolerable on this input. In a typical setup, this signal can be
provided by the MC44011.
Sync amplifier output.
Power connection to the sync separator and amplifier.
Video signal input to the sync separator.
Fed by the external clock divider. Sets the multiplication ratio of the loop in multiples of the F ref
frequency. Negative edge sensitive.
See loop filter calculations at the end of this document.
PIN FUNCTION DESCRIPTION
CIRCUIT DESCRIPTION
MC44145
frequency, line locked clock that is used for video sampling
and digitizing.
drive capability of two LSTTL loads.
current. The charge pump is driven by the phase comparator.
comparator” sequential circuit.
means of an external divider, thus setting the synthesized
frequency. This divider could be implemented in discrete
logic or be a part of an ASIC subsystem.
Phase and Frequency Comparator
which expects a reference frequency at line rate and that is
rising edge sensitive, and NBACK which comes from the
external divider and is falling edge sensitive.
controlled by applying suitable voltage on the appropriate
pins (respectively, NPD Gain and Div 2 EN).
The clock output is a LSTTL–like buffer which has a limited
The VCO is driven from a charge pump with selectable
The phase comparator is a type IV “phase and frequency
The clock generator, the heart of a PLL, is to be closed by
The phase comparator is fed from two input buffers, F ref
Charge pump current and output divider action are
2.0 V; switched out for
Description
2.0 V, high current for
MOTOROLA ANALOG IC DEVICE DATA
0.5 V.
0.5 V.