STA014B STMICROELECTRONICS [STMicroelectronics], STA014B Datasheet - Page 10

• Manufacturer Part Number: STA014B
• Description: MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM AND SRS WOWO POSTPROCESSING CAPABILITY
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA014-STA014B-STA014T
Figure 8. Serial Input Interface Clocks
3. INTERFACE DESCRIPTION
3.1 - Serial Input Interface
STA014 receives the input data (MSB first)
through the Serial Input Interface (Fig.7). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Se-
rial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock. The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. For proper operation BIT_EN line
should be toggled only when SCKR is stable low
(for both SCLK_POL configuration)8The possible
configurations are described in Fig. 8.
3.2 - GPSO Output Interface
In order to retrieve ADPCM encoded data a Gen-
eral Purpose Serial Output interface is available
(in TQFP44 and LFBGA64 packages only). The
maximum frequency for GPSO_SCKR clock is
Figure 9. PCM Output Formats
Table 1: MPEG Sampling Rates (KHz)
10/45
MPEG 1
44.1
48
32
LRCKT
SDO
SDO
SDO
SDO
LRCKT
SDO
SDO
BIT_EN
SCKR
SCKR
SDI
0
M
S
M
S
L
S
32 SCLK Cycles
16 SCLK Cycles
MSB
M
S
0
L
S
M
S
M
S
L
S
0
DATA VALID
0
L
S
L
S
M
S
L
S
0
M
S
M
S
L
S
MSB
32 SCLK Cycles
16 SCLK Cycles
M
S
0
L
S
M
S
M
S
L
S
0
0
D98AU968A
L
S
L
S
M
S
L
S
MPEG 2
0
22.05
M
S
M
S
L
S
32 SCLK Cycles
16 SCLK Cycles
MSB
M
S
24
16
0
L
S
M
S
M
S
the DSP system clock frequency divided by 3
(i.e. 8.192 MHz @ 24.58MHz). The interface is
based on a simple and configurable 3-lines proto-
col, as described by figure 10.
3.3 - PCM Output Interface
The decoded audio data are output in serial PCM
format. The interface consists of the following sig-
nals:
SDO
SCKT
LRCLK
The output samples precision is selectable from
16 to 24 bits/word, by setting the output precision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONF register.
Figure 8 gives a description of the several
STA014 PCM Output Formats. The sample rates
set decoded by STA014 is described in Table 1.
L
S
0
0
L
S
M
S
L
S
L
S
0
M
S
M
S
L
S
32 SCLK Cycles
MSB
16 SCLK Cycles
M
S
DATA IGNORED
0
DATA
L
S
M
S
M
S
IGNORED
L
S
0
0
L
S
M
S
L
S
L
S
PCM Serial Clock Output
Left/Right Channel Selection Clock
PCM Serial Data Output
32 SCLK Cycles
PCM_FORMAT = 1
PCM_DIFF = 1
PCM_FORMAT = 0
PCM_DIFF = 0
PCM_FORMAT = 0
PCM_DIFF = 1
PCM_FORMAT = 1
PCM_DIFF = 1
16 SCLK Cycles
PCM_ORD = 0
PCM_PREC is 16 bit mode
PCM_ORD = 1
PCM_PREC is 16 bit mode
SCLK_POL=0
SCLK_POL=4
MPEG 2.5
11.025
12
8