ISL41334 INTERSIL [Intersil Corporation], ISL41334 Datasheet - Page 18

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ISL41334

Manufacturer Part Number
ISL41334
Description
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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disables the charge pumps if either port is in RS-232 mode,
so V+ collapses to V
All but 5uA of SHDN I
LB, SP, DE) pull-up resistors (~20µA/resistor), so SHDN I
varies depending on the ISLX1334 configuration. The spec
tables indicate the worst case values, but careful selection of
the configuration yields lower currents. For example, in RS-
232 mode the SP pins aren’t used, so if both ports are
configured for RS-232, floating or tying the SP pins high
minimizes SHDN I
are disabled in SHDN, so driving the DE pins high during this
time also reduces I
On the ISL41334, the SHDN I
decreases. V
rather than V
second stage input isn’t driven to the rail, so some I
current flows. See Figure 21 for details.
When enabling from SHDN in RS-232 mode, allow at least
20µs for the charge pumps to stabilize before transmitting
data. The charge pumps aren’t used in RS-485 mode, so the
transceiver is ready to send or receive data in less than 1µs,
which is much faster than competing devices that require the
charge pump for all modes of operation.
Internal Loopback Mode
Driving the LB pin low places both ports in the loopback
mode, a mode that facilitates implementing board level self
test functions. In loopback, internal switches disconnect the
Rx inputs from the Rx outputs, and feed back the Tx outputs
to the appropriate Rx output. This way the data driven at the
Tx input appears at the corresponding Rx output (refer to
“Typical Operating Circuits”). The Tx outputs remain
connected to their terminals, so the external loads are
reflected in the loopback performance. This allows the
loopback function to potentially detect some common bus
faults such as one or both driver outputs shorted to GND, or
outputs shorted together.
Note that the loopback mode uses an additional set of
receivers, as shown in the “Typical Operating Circuits”.
These loopback receivers are not standards compliant, so
the loopback mode can’t be used to implement a half-duplex
RS-485 transceiver.
If loopback won’t be utilized, the pin can be left disconnected
(thanks to the internal pull-up), or it should be connected to
V
ISL41334 (QFN Package) Special Features
Logic Supply (V
The ISL41334 (QFN) includes a V
inputs (Tx inputs and control pins) and Rx outputs. These
pins interface with “logic” devices such as UARTs, ASICs,
and µcontrollers, and today most of these devices use power
supplies significantly lower than 5V. Thus, a 5V output level
CC
(V
L
for the QFN), through a 1kΩ resistor.
L
CC
powers the input stage and sets its V
. V
CC
CC
CC
L
CC
Pin)
. Likewise in RS-485 mode, the drivers
CC
.
powers the second stage, but the
, and V- collapses to GND.
current is due to control input (ON,
18
CC
increases as V
L
pin that powers the logic
L
ISL81334, ISL41334
OH
CC
at V
CC
L
from a 5V powered dual protocol IC might seriously
overdrive and damage the logic device input. Similarly, the
the logic device’s low V
powered dual protocol input. Connecting the V
power supply of the logic device - as shown in Figure 12 -
limits the ISL41334’s Rx output V
and reduces the Tx and control input switching points to
values compatible with the logic device output levels.
Tailoring the logic pin input switching points and output levels
to the supply voltage of the UART, ASIC, or µcontroller
eliminates the need for a level shifter/translator between the
two ICs.
V
switching points may not provide enough noise margin when
V
various V
particular V
L
L
can be anywhere from V
< 1.8V. Table 5 indicates typical V
FIGURE 12. USING V
V
1.65V
GND
GND
1.8V
2.0V
2.5V
3.3V
L
TABLE 5. V
L
V
V
ISL81334
ISL41334
values so the user can ascertain whether or not a
CC
CC
L
(V)
voltage meets his needs.
= +5V
= +5V
R
R
D
D
V
A
A
Y
L
Y
IH
V
V
V
V
AND V
IH
IH
OH
OH
OH
L
≥ 2V
= 0.9V
PIN TO ADJUST LOGIC LEVELS
= 5V
= 2V
might not exceed the V
CC
V
V
IL
V
OH
OH
0.79
0.82
0.87
0.99
1.19
IH
down to 1.65V, but the input
vs. V
≤ 2V
≤ 2V
(V)
OH
UART/PROCESSOR
UART/PROCESSOR
L
to V
IH
R
T
R
T
FOR V
XD
XD
XD
XD
V
V
and V
CC
CC
L
(see Figure 15),
= +2V
= +2V
CC
DIODE
DIODE
ESD
GND
ESD
GND
IL
L
December 20, 2005
= 5V
values for
pin to the
V
0.50
0.60
0.69
0.86
1.05
IL
IH
(V)
of a 5V
FN6202.1

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