SAF-XC161CS-32F20F INFINEON [Infineon Technologies AG], SAF-XC161CS-32F20F Datasheet - Page 67
SAF-XC161CS-32F20F
Manufacturer Part Number
SAF-XC161CS-32F20F
Description
16-Bit Single-Chip Microcontroller with C166SV2 Core
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.SAF-XC161CS-32F20F.pdf
(87 pages)
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4.4
4.4.1
The internal operation of the XC161 is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC161.
Figure 14
Note: The example for PLL operation shown in
The used mechanism to generate the master clock is selected by register PLLCON.
Data Sheet
the example for prescaler operation refers to a divider factor of 2:1.
Phase Locked Loop Operation (1:N)
f
f
Direct Clock Drive (1:1)
f
f
Prescaler Operation (N:1)
f
f
OSC
MC
OSC
MC
OSC
MC
AC Parameters
Definition of Internal Timing
Generation Mechanisms for the Master Clock
f
MC
can be generated from the oscillator clock signal
65
Figure 14
refers to a PLL factor of 1:4,
TCM
Electrical Parameters
TCM
TCM
XC161CS-32F
MCT05555
Derivatives
V1.2, 2006-08
f
MC
f
OSC
.
f
MC
via
.
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