SAF-C161K-LM3V INFINEON [Infineon Technologies AG], SAF-C161K-LM3V Datasheet - Page 57

• Manufacturer Part Number: SAF-C161K-LM3V
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
2)
3)
Data Sheet
RW-delay and
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
1)
A
1)
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
t
53
68
55
57
t
A
+
CC -6 +
CC 6 +
SR –
SR –
t
C
+
min.
t
F
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
t
t
F
= 25 MHz
F
53
max.
20 +
0 +
–
–
t
F
t
F
1 / 2TCL = 1 to 25 MHz
min.
–
–
-6 +
TCL - 14
+
Variable CPU Clock
t
F
t
F
max.
2TCL - 20
+ 2
1)
TCL - 20
+ 2
1)
–
–
t
t
A
A
V2.0, 2001-01
+
+
t
t
F
F
C161O
C161K
Unit
ns
ns
ns
ns