MC68HC908GZ8 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GZ8 Datasheet - Page 75

• Manufacturer Part Number: MC68HC908GZ8
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Special Modes
4.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
4.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
4.7.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the OSCSTOPENB bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
4.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See
16.7.3 Break Flag Control
Register.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
4.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
4.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz
= 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise hit, the
acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz
step input.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
75