MC68HC908AP64_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908AP64_07 Datasheet - Page 237

• Manufacturer Part Number: MC68HC908AP64_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

14.6.2
MMEN — MMIIC Enable
MMIEN — MMIIC Interrupt Enable
MMCLRBB — MMIIC Clear Busy Flag
MMTXAK — MMIIC Transmit Acknowledge Enable
REPSEN — Repeated Start Enable
MMCRCBYTE — MMIIC CRC Byte
Freescale Semiconductor
This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags
will restore to its power-on default states. Reset clears this bit.
When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF flags are enabled to generate an
interrupt request to the CPU. When MMIEN is cleared, the these flags are prevented from generating
an interrupt request. Reset clears this bit.
Writing a logic 1 to this write-only bit clears the MMBB flag. MMCLRBB always reads as a logic 0.
Reset clears this bit.
This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock
bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th
clock bit. Reset clears this bit.
This bit is set to enable repeated START signal to be generated when in master mode transfer
(MMAST = 1). The REPSEN bit is cleared by hardware after the completion of repeated START signal
or when the MMAST bit is cleared. Reset clears this bit.
In receive mode, this bit is set by software to indicate that the next receiving byte will be the packet
error checking (PEC) data.
In master receive mode, after completion of CRC generation on the received PEC data, an
acknowledge signal is sent if MMTXAK = 0; no acknowledge is sent If MMTXAK = 1.
In slave receive mode, no acknowledge signal is sent if a CRC error is detected on the received PEC
data. If no CRC error is detected, an acknowledge signal is sent if MMTXAK = 0; no acknowledge is
sent If MMTXAK = 1.
1 = MMIIC module enabled
0 = MMIIC module disabled
1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will generate interrupt request to CPU
0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not generate interrupt request to CPU
1 = Clear MMBB flag
0 = No affect on MMBB flag
1 = MMIIC does not send acknowledge signals at 9th clock bit
0 = MMIIC sends acknowledge signal at 9th clock bit
1 = Repeated START signal will be generated if MMAST bit is set
0 = No repeated START signal will be generated
MMIIC
Address:
Reset:
Read:
Write:
Control Register 1 (MMCR1)
MMEN
$0049
Bit 7
0
Figure 14-5. MMIIC Control Register 1 (MMCR1)
= Unimplemented
MMIEN
6
0
MC68HC908AP Family Data Sheet, Rev. 4
MMCLRBB
5
0
0
4
0
0
MMTXAK REPSEN
3
0
2
0
MMCRCBYTE
1
0
MMIIC I/O Registers
Bit 0
0
0
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