UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet - Page 23

• Manufacturer Part Number: UJA1075TW/3V3
• Description: High-speed CAN/LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
UJA1075_2
Product data sheet
6.7.1.2 Lowpower/Off modes
and
In CAN Active mode, the transceiver can transmit and receive data via the CANH and
CANL pins. The differential receiver converts the analog data on the bus lines into digital
data which is output on pin RXDC. The transmitter converts digital data generated by a
CAN controller, and input on pin TXDC, to signals suitable for transmission over the bus
lines.
The CAN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit
STBCC = 1 (see
and CANL in Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the CAN transceiver
will be in Off mode if bit STBCC = 0. The CAN transceiver is powered down completely in
Off mode to minimize quiescent current consumption.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI.
A recessive-dominant-recessive-dominant sequence must occur on the CAN bus within
the wake-up timeout time (t
(see
phases). The minimum recessive/dominant bus times for CAN transceiver wake-up
(t
wake(busrec)min
Fig 9.
•
•
•
•
wake-up
the SBC is in Normal mode (MC = 10 or 11)
the transceiver is enabled (bit STBCC = 0; see
V2 is enabled and its output voltage is above its undervoltage threshold, V
or
V2 is disabled but an external voltage source, or V1, connected to pin V2 is above its
undervoltage threshold (see
Figure
CAN wake-up timing diagram
9; note that additional pulses may occur between the recessive/dominant
recessive
and t
All information provided in this document is subject to legal disclaimers.
Table
wake(busdom)min
6). The CAN transceiver can be woken up remotely via pins CANH
Rev. 02 — 27 May 2010
to(wake)
Section
dominant
) to pass the wake-up filter and trigger a wake-up event
) must be satisfied (see
6.6.3)
t
High-speed CAN/LIN core system basis chip
wake
< t
to(wake)
Table
recessive
6)
Table
11).
UJA1075
© NXP B.V. 2010. All rights reserved.
dominant
uvd
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