UJA1069TW PHILIPS [NXP Semiconductors], UJA1069TW Datasheet - Page 34

• Manufacturer Part Number: UJA1069TW
• Description: LIN fail-safe system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
Table 11.
[1]
Table 12.
UJA1069_2
Preliminary data sheet
Bit
12
11 to 5
4
3
2
1
0
Bit
15 and 14
13
12
11 and 10
9
8
7
6 and 5
In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is
automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing
the LTC bit under software control.
Physical Layer Control and Physical Layer Control Feedback register bit description
Special Mode register and Special Mode Feedback register bit description
Symbol
RO
-
LMC
LSC
LDC
LWEN
LTC
Symbol
A1, A0
RRS
RO
-
ISDM
-
-
WDPRE [1:0]
6.12.10 Special Mode register and Special Mode Feedback register
These registers allow configuration of global SBC parameters during start-up of a system
and allow the settings to be read back.
Description
Read Only
reserved
LIN Mode Control
LIN Slope Control
LIN Driver Control
LIN Wake-up Enable
LIN Transmitter
Control
Description
register address
Read Register Select
Read Only
reserved
Initialize Software
Development Mode
reserved
reserved
Watchdog Prescaler
[1]
[1]
Rev. 02 — 5 March 2007
Value
1
0
000 0000 reserved for SBCs with CAN transceiver
1
0
1
0
1
0
1
0
1
0
Value
01
0
1
1
0
0
1
0
0
0
00
01
10
11
Function
read the register selected by RRS without writing to the
Physical Layer Control register
read the register selected by RRS and write to Physical
Layer Control register
LIN Active mode (in Normal mode and Flash mode only)
LIN Active mode disabled
up to 10.4 kbit/s (low slope)
up to 20 kbit/s (normal)
increased LIN driver current capability
LIN driver in conformance with the LIN 2.0 standard
wake-up via the LIN-bus enabled
wake-up via the LIN-bus disabled
LIN transmitter is disabled
LIN transmitter is enabled
Function
select Special Mode register
read the Interrupt Enable Feedback register
read the Special Mode Feedback register
read the register selected by RRS without writing to the
Special Mode register
read the register selected by RRS and write to the
Special Mode register
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
initialization of software development mode
normal watchdog interrupt, reset monitoring and fail-safe
behavior
reserved for SBCs with CAN transceiver
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
watchdog prescale factor 1
watchdog prescale factor 1.5
watchdog prescale factor 2.5
watchdog prescale factor 3.5
LIN fail-safe system basis chip
…continued
UJA1069
© NXP B.V. 2007. All rights reserved.
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