LAN9215I-MT-E2 SMSC [SMSC Corporation], LAN9215I-MT-E2 Datasheet - Page 58

• Manufacturer Part Number: LAN9215I-MT-E2
• Description: Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.5 (07-18-06)
3.15.3
29:16
BITS
31
30
15
14
13
12
Reserved. This bit is reserved. Reads 0.
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
Note 3.16 The LAN9215I host bus interface supports 16-bit bus transfers; internally, all data paths
RX Status Format
are 32-bits wide.
transactions.
Host Read
Order
Last
2nd
1st
Figure 3.18 RX Packet Format
Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Figure 3.18
31
ofs + First Data DWORD
DATASHEET
Optional offset DWORDn
Optional offset DWORD0
Optional Pad DWORD0
Optional Pad DWORDn
Last Data DWORD
describes the host read ordering for pairs of atomic 16-bit
DESCRIPTION
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SMSC LAN9215I
Datasheet