LAN9215I-MT-E2 SMSC [SMSC Corporation], LAN9215I-MT-E2 Datasheet - Page 126

• Manufacturer Part Number: LAN9215I-MT-E2
• Description: Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.5 (07-18-06)
6.7
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
FIFO_SEL
nCS, nRD
Data Bus
In this mode the upper address inputs are not decoded, and any write to the LAN9215I will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9215I . Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note: The “Data Bus” width is 16 bits.
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
TX Data FIFO Direct PIO Writes
A[2:1]
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time (see Note below)
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order. Parameters t
the t
cycle
minimum.
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
DATASHEET
126
csh
and t
csl
must be extended using wait states to meet
MIN
165
32
13
0
7
0
0
TYP
133
MAX
SMSC LAN9215I
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns