LAN9215-MT-E2 SMSC [SMSC Corporation], LAN9215-MT-E2 Datasheet - Page 13

• Manufacturer Part Number: LAN9215-MT-E2
• Description: Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC LAN9215
1.11
1.12
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9215 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9215 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits
wide. The LAN9215 can be interfaced to either Big-Endian or Little-Endian processors.
The LAN9215 also supports the ability to interface to an external PHY device. This interface is
compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the
MII interface and associated signals, please refer to
Switching," on page 41
Host Bus Interface (SRAM Interface)
External MII Interface
for more information.
DATASHEET
13
Section 3.13, "MII Interface - External MII
Revision 1.5 (07-18-06)