LAN9215-MT-E2 SMSC [SMSC Corporation], LAN9215-MT-E2 Datasheet - Page 125

• Manufacturer Part Number: LAN9215-MT-E2
• Description: Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC LAN9215
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nRD
Data Bus
A[7:1]
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
PIO writes are used for all LAN9215 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time (see Note below)
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Parameters t
csh
and t
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
csl
must be extended using wait states to meet the t
DATASHEET
125
MIN
165
32
13
0
7
0
0
TYP
133
Revision 1.5 (07-18-06)
cycle
MAX
minimum.
UNITS
ns
ns
ns
ns
ns
ns
ns