PEB2045-N SIEMENS [Siemens Semiconductor Group], PEB2045-N Datasheet - Page 23

• Manufacturer Part Number: PEB2045-N
• Description: Memory Time Switch CMOS (MTSC)
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 7
Connection Memory Access IA Byte Structure
Bit 7
0
D7
IA7
The following example illustrates how an indirect memory access works.
The instruction sequence
00110000
01010101
11111111
writes the hexadecimal value 55
The instruction sequence
00010010
00000000
10101010
writes the hexadecimal value 200
output.
To read the indirect registers or the CM two sequences of 3 instructions each have to be
programmed.
In the first sequence the PEx 2045 is instructed which register or CM address to read. The data
transferred to the PEx 2045 in this first sequence is of no importance.
With the first write instruction STA:Z is set.
After the first 3 instructions the PEx 2045 needs 900 ns to read the specified location and to write
the result to the IAR. It overwrites the data byte and in the case of a CM-read operation additionally
bits 1 and 0 of the control byte. The status register bit Z is reset after maximally 900 ns. Then 3 read
operations follow. Again, STA:Z is set with the first read instruction. The 3 instructions read 3 bytes
from the IAR. Figure 13b shows this procedure. The data byte and, in the case of a CM-read
operation, the C1 and C0 bits in the control byte show the values read from the indirect registers or
the CM. The K0, K1 bits and the address byte have not changed their values since the proceeding
write instruction sequence.
After the third read operation the PEx 2045 needs another 900 ns to reset the indirect access
mechanism and the Z bit in the status register.
Semiconductor Group
0
D6
IA6
A0 = 1, WR = 0, RD = 1, CS = 0
A0 = 1, WR = 0, RD = 1, CS = 0
K1
D5
IA5
K0
D4
IA4
H
into the clock shift register.
H
into the connection memory location AA
0
D3
IA3
0
D2
IA2
23
D9
D1
IA1
D8
D0
IA0
Bit 0
Control Byte
Data Byte
Address Byte
H
thus tristating the
PEB 2045
PEF 2045