PEB2045-N SIEMENS [Siemens Semiconductor Group], PEB2045-N Datasheet - Page 19
PEB2045-N
Manufacturer Part Number
PEB2045-N
Description
Memory Time Switch CMOS (MTSC)
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.PEB2045-N.pdf
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2.2
The PEx 2045 is programmed via the P interface. It consists of the data bus DB7 … DB0, the
address bit A0, the Write (WR), the Read (RD) and Chip Select (CS) signal, as shown in figure 12.
Figure 12
The PEx 2045 Controlled by a Microprocessor
To perform any register access, CS has to be zero. This pin is provided, so that a single chip can
be activated in an environment where one microprocessor controls many slave processors (see
figure 20).
The PEx 2045 incorporates 4 user programmable registers,
as well as
The mode register is a write only register; the status register is a read only register. CFR, CSR and
CM can be read and written. The single address bit A0 does not offer enough address space to
encode all access possibilities. Therefore the indirect access scheme is used to access the CFR,
CSR and CM. It uses the indirect access register (IAR), which is provided on chip.
Semiconductor Group
the mode register (MOD)
the status register (STA)
the configuration register (CFR) and
the clock shift register (CSR)
the connection memory (CM).
Microprocessor Interface and Registers
19
PEB 2045
PEF 2045
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