LAN8187I SMSC [SMSC Corporation], LAN8187I Datasheet - Page 48

• Manufacturer Part Number: LAN8187I
• Description: High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.6 (02-24-06)
5.3
ENERGYON activated
Auto-Negotiate Complete
Remote Fault Detected
Link Status negated (not asserted)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
ADDRESS
31.9:7
31.4:2
31.10
31.11
31.6
31.5
31.1
31.0
The Management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. It generates an active low interrupt signal on the nINT output whenever certain events
are detected. Reading the Interrupt Source register (Register 29) shows the source of the interrupt,
and clears the interrupt output signal. The Interrupt Mask register (Register 30) enables for each
source to set (LOW) the nINT, by asserting the corresponding mask bit. The Mask bit does not mask
the source bit in register 29. At reset, all bits are masked (negated). The nINT is an asynchronous
output.
Interrupt Management
Scramble Disable
Speed Indication
INTERRUPT SOURCE
MII_CLK_SEL
Enable 4B5B
Reserved
Reserved
Reserved
GPO[2:0]
Table 5.44 Register 31 - PHY Special Control/Status (continued)
NAME
MII Mode:
0 = MII Clock of 25MHz. (Default)
1 = Can be written in MII mode to set the interface
speed to 50MHz.
RMII Mode:
0 = Invalid (Do not clear this bit if in RMII mode)
1 = RMII Clock of 50 MHz (Default)
Note:
Reserved
General Purpose Output connected to signals
GPO[2:0]
0 = Bypass encoder/decoder.
1 = enable 4B5B encoding/decoding.
Write as 0, ignore on Read.
HCDSPEED value:
[001]=10Mbps Half-duplex
[101]=10Mbps Full-duplex
[010]=100Base-TX Half-duplex
[110]=100Base-TX Full-duplex
Write as 0; ignore on Read
0 = enable data scrambling
1 = disable data scrambling,
MAC Interface must be configured in MII mode.
Defaults low (0) always in MII mode and high
always in RMII mode.
DATASHEET
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
DESCRIPTION
48
SOURCE/MASK REG BIT #
7
6
5
4
3
2
1
SMSC LAN8187/LAN8187I
MODE
RW
RW
RW
RW
RW
RW
RW
RO
DEFAULT
RMII/MII
depnd’t
Datasheet
mode
000
0
0
1
0
0
0