LAN8187I SMSC [SMSC Corporation], LAN8187I Datasheet
LAN8187I
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LAN8187I Summary of contents
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... LED status indicators Commercial Operating Temperature 0° 70° C Industrial Operating Temperature -40° 85° C version available (LAN8187I) LAN8187-JT FOR 64-PIN, TQFP PACKAGE (GREEN, LEAD-FREE) LAN8187I-JT FOR INDUSTRIAL TEMPERATURE 64-PIN, TQFP PACKAGE (GREEN, LEAD-FREE) SMSC LAN8187/LAN8187I LAN8187/LAN8187I High-Performance MII and RMII 10/100 Ethernet ...
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... NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX 2 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...
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... Receive Data Across the MII/RMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.4 Jabber Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 MAC Interface 4.6.1 MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6.2 RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6.3 MII vs. RMII Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7.1 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.2 Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.3 Disabling Auto-negotiation 4.7.4 Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.9 Internal +1.8V Regulator Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9.1 Disable the Internal +1.8V Regulator 4.9.2 Enable the Internal +1.8V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10 (TX_ER/TXD4)/nINT Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SMSC LAN8187/LAN8187I 3 DATASHEET Revision 0.6 (02-24-06) ...
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... RMII 10/100Base-TX/RX Timings 6.3.1 RMII 100Base-T TX/RX Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 RMII 10Base-T TX/RX Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4 REF_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.5 Reset Timing 6.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.6.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.6.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.6.3 DC Characteristics - Input and Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Chapter 7 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX 4 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...
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... High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX Datasheet List of Figures Figure 1.1 LAN8187/LAN8187I System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 1.2 LAN8187/LAN8187I Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.1 Package Pinout (Top View Figure 4.1 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.3 Relationship Between Received Data and specific MII Signals . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4.4 Direct cable connection vs. Cross-over cable connection Figure 4.5 PHY Address Strapping on LED’ ...
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... List of Tables Table 2.1 LAN8187/LAN8187I 64-PIN TQFP Pinout Table 3.1 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3.2 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.3 Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.4 Boot Strap Configuration Inputs Table 3.5 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.6 10/100 Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.7 Analog References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.8 No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3.9 Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4.2 MII/RMII Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4 ...
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... Table 6.13 MII Bus Interface Signals Table 6.14 LAN Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 6.15 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 6.16 Configuration Inputs Table 6.17 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6.18 Analog References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6.19 Internal Pull-Up / Pull-Down Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6.20 100Base-TX Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 6.21 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7.1 64 Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SMSC LAN8187/LAN8187I 7 DATASHEET Revision 0.6 (02-24-06) ...
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... RMII requires only 6 pins for each MAC to PHY interface plus one common reference clock. The MII requires 16 pins for each MAC to PHY interface. The SMSC LAN8187/LAN8187I is capable of running in RMII mode. Please refer to the RMII consortium for more information on the RMII standard http://www.rmii-consort.com. ...
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... TX_EN 100M Rx TX_ER Logic TX_CLK RXD[0..3] RX_DV Receive Section RX_ER RX_CLK 10M Rx CRS Logic COL/CRS_DV MDC MDIO Figure 1.2 LAN8187/LAN8187I Architectural Overview SMSC LAN8187/LAN8187I Auto- 10M Tx 10M Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter DSP System: Analog-to- Clock Digital Data Recovery ...
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... NC NC VDD33 VDD_CORE VSS2 SPEED100/PHYAD0 16 Figure 2.1 Package Pinout (Top View) Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX LAN8187/LAN8187I 10 DATASHEET Datasheet 48 CRS COL/CRS_DV nINT/TX_ER/TXD4 TXD3 TXD2 VDDIO TXD1 TXD0 VSS5 TX_EN TX_CLK AMDIX_EN CH_SELECT RX_ER/RXD4 RX_CLK 33 RX_DV SMSC LAN8187/LAN8187I ...
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... High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX Datasheet Table 2.1 LAN8187/LAN8187I 64-PIN TQFP Pinout PIN NO. PIN NAME 1 GPO0/MII 2 GPO1/PHYAD4 3 GPO2 4 MODE0 5 MODE1 6 MODE2 7 VSS1 TEST0 10 TEST1 VDD33 14 VDD_CORE 15 VSS2 16 SPEED100/PHYAD0 17 LINK/PHYAD1 ACTIVITY/PHYAD2 20 FDUPLEX/PHYAD3 XTAL2 23 CLKIN/XTAL1 ...
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... I Transmit Enable: Indicates that valid data is presented on the TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0] have valid data. O Transmit Clock: 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. Note: This signal is not used in RMII Mode 12 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...
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... RXD2 RXD3/ nINTSEL RX_ER/ RXD4 RX_CLK COL/CRS_DV SMSC LAN8187/LAN8187I Table 3.1 MII Signals (continued) TYPE O Receive Data 0: Bit 0 of the 4 data bits that are sent by the PHY in the receive path. O Receive Data 1: Bit 1 of the 4 data bits that are sent by the PHY in the receive path ...
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... This signal is mux’d with ACTIVITY I/O PHY Address Bit 1: set the default address of the PHY. Note: This signal is mux’d with LINK I/O PHY Address Bit 0: set the default address of the PHY. Note: This signal is mux’d with SPEED100 14 DATASHEET Datasheet a SMSC LAN8187/LAN8187I ...
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... CH_SELECT GPO0/MII a.On nRST transition high, the PHY latches the state of the configuration pins in this table. SIGNAL NAME nINT nRST SMSC LAN8187/LAN8187I TYPE DESCRIPTION I PHY Operating Mode Bit 2: set the default MODE of the PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page the MODE options ...
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... Transmit Data: 100Base-TX or 10Base-T differential transmit outputs to magnetics. AI Receive Data: 100Base-TX or 10Base-T differential receive inputs from magnetics. AI Receive Data: 100Base-TX or 10Base-T differential receive inputs from magnetics. Table 3.7 Analog References TYPE DESCRIPTION AI Connects to reference resistor of value 12.4K-Ohm, 1% connected as described in the Analog Layout Guidelines. 16 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...
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... AVDD2 AVDD3 AVSS1 AVSS2 AVSS3 AVSS4 VDD_CORE VDD33 VDDIO VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 SMSC LAN8187/LAN8187I Table 3.8 No Connect Signals TYPE DESCRIPTION No Connect Table 3.9 Power Signals TYPE +3.3V Analog Power POWER +3.3V Analog Power POWER +3.3V Analog Power POWER Analog Ground POWER Analog Ground ...
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... rive Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 18 DATASHEET Datasheet S cra its tic Table 4.1. Each 4-bit data-nibble SMSC LAN8187/LAN8187I ...
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... CRS if following /T/, else assertion of RX_ER 00100 H Transmit Error Symbol 00110 V INVALID, RX_ER if during RX_DV 11001 V INVALID, RX_ER if during RX_DV 00000 V INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV SMSC LAN8187/LAN8187I Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 ...
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... The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX RECEIVER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID 20 DATASHEET Datasheet TRANSMITTER INTERPRETATION SMSC LAN8187/LAN8187I ...
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... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN8187/LAN8187I 100M PLL 25MHz 4B/5B ...
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... RX_CLK RX_DV RXD Figure 4.3 Relationship Between Received Data and specific MII Signals Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX data data data data data data data data 22 DATASHEET Datasheet Idle T R SMSC LAN8187/LAN8187I ...
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... Detect," on page For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the LAN8187/LAN8187I. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted. Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “ ...
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... MHz RX_CLK. For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX 24 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...
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... The PHY drives RX_ER high when a receive error is detected. 4.6.2 RMII The SMSC LAN8187/LAN8187I supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase ...
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... MII vs. RMII Configuration The LAN8187/LAN8187I must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done through the GPO0/MII pin. MII or RMII mode selection is latched on the rising edge of the internal reset (nreset) based on the strapping of the GPO0/MII pin. To select MII mode, float the GPO0/MII pin. To select RMII mode, pull- high with an external resistor (see VDD33 ...
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... Serial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register (Register 5). The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. SMSC LAN8187/LAN8187I Table 4.2, "MII/RMII Signal Table 4.2 MII/RMII Signal Mapping MII MODE TXD0 ...
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... Register 0, bit 9 must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN8187/LAN8187I does not support “Next Page” capability. Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX ...
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... Parallel Detection If the LAN8187/LAN8187I is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. ...
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... Figure 4.4 Direct cable connection vs. Cross-over cable connection. 4.9 Internal +1.8V Regulator Disable Part of the LAN8187/LAN8187I SMSC flexPWR regulator. This further increases the power savings as a more efficient external switching regulator can provide the necessary +1.8v to the internal PHY circuitry. 4.9.1 Disable the Internal +1.8V Regulator To disable the +1.8v internal regulator, a pulldown strapping resistor (see Configuration Resistors,” ...
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... Figure 4.5 PHY Address Strapping on LED’s 4.12 Variable Voltage I/O The Digital I/O pins on the LAN8187/LAN8187I are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1. +3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as for two aspects of their design ...
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... Interrupt 4.13.1 Serial Management Interface (SMI) The Serial Management Interface is used to control the LAN8187/LAN8187I and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers allowed by the specification. Non-supported registers (7 to 15) will be read as hexadecimal “ ...
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... Start of OP Preamble Frame Code Figure 4.7 MDIO Timing and Frame Structure - WRITE Cycle SMSC LAN8187/LAN8187I 53. Read Cycle PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address ...
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Chapter 5 Registers Rese Loopbac Speed A Select Enable 100Bas 100Base- 100Base- 10Base- e- Full Half Full Duplex Duplex Duplex PHY ID ...
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Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended Next Reserve Remot Reserve Symmetric Page Pause Fault Operation Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended ...
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Table 5.9 Register 8 (Extended ...
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Table 5.17 Silicon Revision Register 16: Vendor-Specific Reserved Table 5.18 Mode Control/ Status Register 17: Vendor-Specific Reserved FASTRIP EDPWRDOWN Reserved LOWSQEN ...
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Table 5.24 Special Control/Status Indications Register 27: Vendor-Specific Reserved SWRST_FA SQEOF ST F Table 5.20 ...
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Table 5.25 Special Internal Testability Control Register 28: Vendor-Specific Table 5.26 Interrupt Source Flags Register 29: Vendor-Specific Reserved AMDIXCTR Reserve CH_SELEC Table 5.28 ...
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... NASR = Not Affected by Software Reset Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX Table 5.29 SMI Register Mapping DESCRIPTION 40 DATASHEET Datasheet Group Basic Basic Extended Extended Extended Extended Extended Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific SMSC LAN8187/LAN8187I ...
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... Duplex 1.11 10Base-T Half Duplex 1.10:6 Reserved 1.5 Auto-Negotiate Complete 1.4 Remote Fault SMSC LAN8187/LAN8187I Table 5.30 Register 0 - Basic Control DESCRIPTION when setting this bit do not set other bits in this register. (overrides 0.13 and 0.8) Table 5.31 Register 1 - Basic Status DESCRIPTION able ability with full duplex, ...
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... Both Symmetric PAUSE and Asymmetric PAUSE toward local device able ability This Phy does not support 100Base-T4. 42 DATASHEET Datasheet MODE DEFAULT MODE DEFAULT RW 0007h MODE DEFAULT RW 30h RW 0Bh RW 1h MODE DEFAULT R SMSC LAN8187/LAN8187I ...
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... Duplex 5.7 100Base-TX 5.6 10Base-T Full Duplex 5.5 10Base-T 5.4:0 Selector Field SMSC LAN8187/LAN8187I DESCRIPTION with full duplex full duplex ability able ability 1 = 10Mbps with full duplex 10Mbps with full duplex ability 1 = 10Mbps able 10Mbps ability [00001] = IEEE 802.3 DESCRIPTION 1 = “ ...
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... Management Data Preamble Bypass: 0 – detect SMI packets with Preamble 1 – detect SMI packets without preamble 44 DATASHEET Datasheet MODE DEFAULT MODE DEFAULT 0001 RO 0 MODE DEFAULT RW 0 RW, 0 NASR SMSC LAN8187/LAN8187I ...
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... Reserved 18.9 PLLBP 18.8 ADCBP SMSC LAN8187/LAN8187I DESCRIPTION Force the module to the FAR Loop Back mode, i.e. all the received packets are sent back simultaneously (in 100Base-TX only). This bit is only active in RMII mode. In this mode the user needs to supply a 50MHz clock to the PHY. This mode works even if MII Isolate (0 ...
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... Auto-negotiation “ARB” State-machine state DESCRIPTION Do not write to this register. Ignore on read. 46 DATASHEET Datasheet MODE DEFAULT RW, for more NASR RW, PHYAD NASR MODE DEFAULT RW, 0 NASR RW, 0 NASR 1011b MODE DEFAULT RW N/A SMSC LAN8187/LAN8187I ...
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... Table 5.44 Register 31 - PHY Special Control/Status ADDRESS NAME 31.15 Reserved 31.14 Reserved 31.13 Special 31.12 Autodone SMSC LAN8187/LAN8187I DESCRIPTION Ignore on read ENERGYON generated 0 = not source of interrupt 1 = Auto-Negotiation complete 0 = not source of interrupt 1 = Remote Fault Detected 0 = not source of interrupt 1 = Link Down (link status negated not source of interrupt 1 = Auto-Negotiation LP Acknowledge ...
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... Full-duplex [010]=100Base-TX Half-duplex [110]=100Base-TX Full-duplex Write as 0; ignore on Read 0 = enable data scrambling 1 = disable data scrambling, SOURCE/MASK REG BIT # 48 DATASHEET Datasheet MODE DEFAULT RW RMII/MII mode depnd’ 000 SMSC LAN8187/LAN8187I ...
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... Link Integrity Test The LAN8187/LAN8187I performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED. ...
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... For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25 MHz if auto-negotiation is enabled. Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX The first and possibly the second packet 50 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...
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... The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address latched in on reset. The LAN8187/LAN8187I senses each Phy address bit and changes the polarity of the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active- low. If the address bit is set as level “ ...
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... Power-Down mode. 111 All capable. Auto-negotiation enabled. Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX Table 5.45 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES REGISTER 0 [13,12,10,8] 52 DATASHEET Datasheet REGISTER 4 [8,7,6,5] 0000 N/A 0001 N/A 1000 N/A 1001 N/A 1100 0100 1100 0100 N/A N/A X10X 1111 SMSC LAN8187/LAN8187I ...
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... PHY) MDIO (Write to PHY) PARAMETER DESCRIPTION T1.1 MDC minimum cycle time T1.2 MDC to MDIO (Write) delay T1.3 MDIO (Read) to MDC setup T1.4 MDIO (Read) to MDC hold SMSC LAN8187/LAN8187I T1.1 T1.2 Valid Data T1.3 T1.4 Valid Data Figure 6.1 SMI Timing Diagram Table 6.1 SMI Timing Values MIN TYP 400 0 ...
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... DESCRIPTION T2.1 Receive signals setup to RX_CLK rising T2.2 Receive signals hold from RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX Valid Data T2.1 T2.2 MIN TYP MAX DATASHEET Datasheet UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187I ...
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... Transmit signals setup to TX_CLK rising T3.2 Transmit signals hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle 6.2.2 MII 10Base-T TX/RX Timings 6.2.2.1 10M MII Receive Timing RX_CLK RXD[3:0] RX_DV RX_ER Figure 6.4 10M MII Receive Timing Diagram SMSC LAN8187/LAN8187I Valid Data T3.1 T3.2 MIN TYP MAX Valid Data T4.1 T4.2 55 DATASHEET ...
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... Transmit signals hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX MIN TYP MAX Valid Data T5.1 T5.2 MIN TYP MAX DATASHEET Datasheet UNITS NOTES ns ns MHz % ns UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187I ...
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... Figure 6.6 100M RMII Receive Timing Diagram Table 6.6 100M RMII Receive Timing Values PARAMETER DESCRIPTION T6.1 Rising edge of REF_CLK to receive signals output valid T6.2 Rising edge of REF_CLK to receive signals output not valid REF_CLK frequency SMSC LAN8187/LAN8187I Valid Data T6.1 T6.2 MIN TYP MAX UNITS ...
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... RMII 10Base-T TX/RX Timings 6.3.2.1 10M RMII Receive Timing REF_CLK RXD[1:0] CRS_DV Figure 6.8 10M RMII Receive Timing Diagram Revision 0.6 (02-24-06) High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX Valid Data T8.1 T8.2 MIN TYP MAX UNITS Valid Data T9.1 T9.2 58 DATASHEET Datasheet NOTES ns ns MHz SMSC LAN8187/LAN8187I ...
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... Transmit signals setup to REF_CLK rising T10.2 Transmit signals hold after REF_CLK rising 6.4 REF_CLK Timing PARAMETER DESCRIPTION REF_CLK frequency REF_CLK Frequency Drift REF_CLK Duty Cycle REF_CLK Jitter SMSC LAN8187/LAN8187I MIN TYP 2 50 Valid Data T10.1 T10.2 MIN TYP 4 Table 6.10 REF_CLK Timing Values MIN ...
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... High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX T6.1 T6.2 T6.3 T6.4 Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values MIN TYP 100 200 400 20 60 DATASHEET Datasheet MAX UNITS NOTES 800 ns 20 clock cycles for 25 MHz clock or 40 clock cycles for 50MHz clock SMSC LAN8187/LAN8187I ...
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... DC Characteristics 6.6.1 Operating Conditions VDD33 Supply Voltage VDDIO Supply Voltage Operating Temperature Industrial Operating Temperature -40°C to +85°C version available (LAN8187I) 6.6.2 Power Consumption 6.6.2.1 Power Consumption Device Only Power measurements taken over the operating conditions specified. See of the power down modes. 3.3v CURRENT (mA) ...
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... DATASHEET Datasheet +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0 +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V 3.6V SMSC LAN8187/LAN8187I ...
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... VDDIO – +0.4 V PHYAD2 VDDIO – +0.4 V PHYAD3 VDDIO – +0.4 V PHYAD4 MODE0 VDDIO – +0.4 V MODE1 VDDIO – +0.4 V MODE2 VDDIO – +0.4 V REG_EN VDDIO – +0.4 V MII SMSC LAN8187/LAN8187I Table 6.14 LAN Interface Signals “10BASE-T Transceiver Characteristics,” on page Table 6.15 LED Signals ...
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... V +0 Table 6.18 Analog References PULL-UP OR PULL-DOWN Pull-down Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down 64 DATASHEET Datasheet +0.4 V VDDIO – +0.4 V +0.4 V 3.7 V +0.4 V VDDIO – +0 SMSC LAN8187/LAN8187I ...
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... Offset from 16 nS pulse width at 50% of pulse peak Note 6.4 Measured differentially. Table 6.21 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Min/max voltages guaranteed as measured with 100 Ω resistive load. Note 6.5 SMSC LAN8187/LAN8187I PULL-UP OR PULL-DOWN Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down ...
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... MAX REMARKS 1.60 Overall Package Height 0.15 Standoff 1.45 Body Thickness 12.20 X Span 10.20 X body Size 12.20 Y Span 10.20 Y body Size 0.20 Lead Frame Thickness 0.75 Lead Foot Length ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.27 Lead Width ~ Lead Shoulder Radius 0.20 Lead Foot Radius 0.08 Coplanarity 66 DATASHEET Datasheet SMSC LAN8187/LAN8187I ...