ISP1505C NXP [NXP Semiconductors], ISP1505C Datasheet
ISP1505C
Related parts for ISP1505C
ISP1505C Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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... ISP1505A; ISP1505C ULPI Hi-Speed USB host and peripheral transceiver Rev. 03 — 26 August 2008 1. General description The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin Interface (ULPI) Specifi ...
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... N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1505ABS) and 26 MHz (ISP1505CBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I Flexible system integration and very low current consumption, optimized for portable ...
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... MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Package Name Description HVQFN24 plastic thermal enhanced very thin quad flat package; ...
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... EXTERNAL BUS GLOBAL POWER-ON RESET RESET PLL GLOBAL CLOCKS CRYSTAL OSCILLATOR ISP1505 interface voltage internal power V REF VOLTAGE REGULATOR Rev. 03 — 26 August 2008 ISP1505A; ISP1505C 6 DP HIGH-SPEED USB ATX TERMINATION 5 DM RESISTORS V BUS COMPARATORS BUS FAULT SRP CHARGE AND DISCHARGE ...
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... FAULT (input) — Input pin for the external V signal. If this pin is not used as either tolerant 3.3 V regulator output crystal oscillator or clock input crystal oscillator output Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 18 DATA6 17 DATA7 16 NXT ISP1505 ...
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... PCB ground Section 7.10. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver power switch or external charge BUS . CC(I/O) Section 16 ...
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... Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed • Squelch circuit to detect high-speed bus activity ISP1505A_ISP1505C_3 Product data sheet source control BUS monitoring, charging and discharging Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Section 9. © NXP B.V. 2008. All rights reserved ...
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... During power-up expected that the comparator output will be ignored. ISP1505A_ISP1505C_3 Product data sheet high-speed bus terminations on DP and DM for peripheral and host modes Section 16. . Any voltage on V A_VBUS_VLD Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Table 7. CC < 3 valid comparator, session valid BUS voltage level ...
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... The data bus can be reconfigured to carry various data types, as given in Section ISP1505A_ISP1505C_3 Product data sheet . hys(B_SESS_VLD) power. First, the B-device makes sure that V Section 9. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver is below the B-device BUS . B_SESS_END is fully discharged from the BUS by setting the CHRG_VBUS BUS ...
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... BUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Section , must be connected between RREF RREF 16 ...
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... V BUS pullup Section 16. BUS state in RXCMD is not 11b), it must disable the external BUS Rev. 03 — 26 August 2008 ISP1505A; ISP1505C Section 16. . CC(I/ required when PSW_N is used. This power source by setting the BUS power source. If the link detects an © ...
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... This acts as a ground to all circuits in the ISP1505. To ensure correct operation of the ISP1505, GND must be soldered to the cleanest ground available. ISP1505A_ISP1505C_3 Product data sheet ULPI HS USB host and peripheral transceiver 9.3.1. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C © NXP B.V. 2008. All rights reserved ...
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... DIR changes value. This is called the turnaround cycle. Data lines have fixed direction and different meaning in low-power and serial modes. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 15. A description of the ULPI pin behavior in Section 9. ...
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... NXT is not used in low-power or serial mode. Description combinatorial LINESTATE0 directly driven by the analog receiver combinatorial LINESTATE1 directly driven by the analog receiver Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver supply (see Table CC 44). ...
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... O reserved; the ISP1505 will drive this pin to LOW Table Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 5. To enter 6-pin serial mode, the link sets 6. To enter 3-pin serial mode, the link sets the © NXP B.V. 2008. All rights reserved. ...
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... Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 7. Resistor setting signals are defined as follows: Internal resistor settings DM_PULL RPU_ RPD_ DOWN DP_EN DP_EN ...
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... Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver …continued Internal resistor settings DM_PULL RPU_ RPD_ DOWN DP_EN DP_EN ...
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... POR(trip) w(REG1V8_L PORP Internal power-on reset timing shows a typical start-up sequence. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver , for at least POR(trip) , and then rises above V POR(trip Figure 3 shows a possible curve of REG1V8. The , another POR pulse is ...
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... The link may start to detect DIR status level. If DIR is detected as LOW for three clock cycles, the link may send a RESET command. The ULPI interface is ready for use. ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 03 — 26 August 2008 © NXP B.V. 2008. All rights reserved ...
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... If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will startup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver D internal reset ...
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... ISP1505 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit in the OTG Control register and the IND_PASSTHRU bit in the Interface Control register to logic 1. For details, see ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Hi-Z (link must drive) Hi-Z (input) Hi-Z (link must drive) ...
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... REGW 10 1111b EXTR XX XXXXb REGR Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Table 8 Command description No operation. 00h is the idle value of the data bus. The link must drive NOOP by default. Transmit USB data that does not have a PID, such as chirp and resume signaling ...
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... HS_Differential_Receiver_Output invalid !squelch and !HS_Differential_Receiver_Output invalid invalid Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Section 9.5.2.1. state, see Section BUS Section 9.5.2.4. Back-to-back RXCMDs turnaround RXCMD RXCMD © NXP B.V. 2008. All rights reserved. ...
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... BUS A_VBUS_VLD V V BUS A_VBUS_VLD and FAULT share the same pin and cannot be simultaneously used. BUS 9.5.2.3. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Chirp squelch !squelch and HS_Differential_Receiver_Output !squelch and !HS_Differential_Receiver_Output invalid state field in the RXCMD is an encoding of the ...
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... external circuit must be used to BUS Standard peripherals must be able to detect sufficient level for operation. SESS_VLD must be enabled to detect the Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver (0, X) complement output ( ...
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... When the ISP1505 has detected a SYNC pattern on the USB bus, it signals an When the ISP1505 has detected an error while receiving a USB packet, it HostDisconnect is encoded into the RxEvent field of the RXCMD. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver can connect the V power to the ISP1505 V BUS pulsing SRP ...
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... TXCMD (EXTW (REGR) extended immediate register write register read shows the sequence of events for USB reset and high-speed detection Table 11. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TXCMD (EXTW extended register read Figure 9 004aaa710 does not © ...
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... USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver . If the peripheral is in low-power mode, it must wake 0 Rev. 03 — 26 August 2008 © ...
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... K (10b) (00b) TXCMD NOPID K K ... (HS) 10 (chirp) squelch peripheral chirp K (10b) (00b) Rev. 03 — 26 August 2008 ISP1505A; ISP1505C host chirp TXCMD (REGW) NOPID K J ... K J host chirp K (10b) or chirp J (01b) RXCMDs TXCMD (REGW ...
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... Table 16 for correct USB system operation. Examples of high-speed Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Figure 10. For details on USB ISP1505 ISP1505 ISP1505 asserts DIR, sends sends ...
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... Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) EOP link decision time ( clocks) Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver IDLE (one to two clocks) © NXP B.V. 2008. All rights reserved. ...
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... ISP1505A_ISP1505C_3 Product data sheet USB interpacket delay (8 to 192 high-speed bit times) IDLE N turnaround link decision time ( clocks) Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TXCMD TX start delay (one to two clocks) Figure 13. SYNC D0 D1 004aaa713 © ...
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... PRE ID DP and DM timing is not to scale. illustrates how a host or a hub places a full-speed or low-speed peripheral into Figure 14 timing is not to scale, and does not show all RXCMD Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver D1 D0 IDLE (min LS D0 ...
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... ISP1505A_ISP1505C_3 Product data sheet suspend TXCMD TXCMD (REGW) NOPID J LINESTATE J LINESTATE K 00b J illustrates how a host or a hub places a high-speed enabled peripheral into Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver EOP resume K K ... K TXCMD K 10b K SE0 J SE0 ...
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... The peripheral link sees terminations (TERMSELECT is set to 0b). The host link sets Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver terminations, and enables the 1.5 k terminations (TERMSELECT is set to © NXP B.V. 2008. All rights reserved. ...
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... ULPI HS USB host and peripheral transceiver FS suspend TXCMD TXCMD (REGW) NOPID 01b 00b FS J (01b) LINESTATE K LINESTATE J 01b 00b FS J (01b) Rev. 03 — 26 August 2008 ISP1505A; ISP1505C resume K HS idle TXCMD ... (REGW) 00b 10b 00b FS K (10b) SQUELCH (00b) TXCMD ...
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... SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 03 — 26 August 2008 © NXP B.V. 2008. All rights reserved ...
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... EOP when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TXCMD TXCMD ...
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... The following subsections describe how to use the ISP1505 OTG components. ISP1505A_ISP1505C_3 Product data sheet ULPI HS USB host and peripheral transceiver 00h 00h 00h 80h PID SYNC PID BUS Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ... ... D D FEh DATA PAYLOAD EOP IDLE 004aab125 power supply and BUS © ...
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... B-device to discharge V DN(VBUS) BUS is below V BUS B_SESS_END and Figure 19 provide examples of 6-pin serial mode and 3-pin serial mode, Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver , V A_VBUS_VLD A_SESS_VLD and V are combined into B_SESS_VLD Section 7.6. Changes in comparator values Section 9 ...
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... DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 19. Example of transmit followed by receive in 3-pin serial mode ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver TRANSMIT DATA EOP TRANSMIT DATA SYNC EOP Rev. 03 — 26 August 2008 RECEIVE SYNC ...
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... DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 03 — 26 August 2008 © NXP B.V. 2008. All rights reserved ...
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... Size Address (6 bit) (bit) [1] [2] [ 00h to 3Fh 8 40h to FFh Rev. 03 — 26 August 2008 ISP1505A; ISP1505C References [3] [ Section 10.1.1 on page 05h 06h Section 10.1.2 on page 44 08h 09h Section 10.1.3 on page 45 0Bh 0Ch Section 10.1.4 on page 46 ...
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... Description 15h Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h Table 23 RESET OPMODE[1: R/W/S/C R/W/S/C Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Table 20. Table 21. Table 22 TERM XCVRSELECT[1:0] SELECT ...
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... Reset 0 Access R/W/S/C R/W/S/C ISP1505A_ISP1505C_3 Product data sheet 7. Table IND_ reserved COMPL R/W/S/C R/W/S/C Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver provides the bit allocation of the register CLOCK_ reserved 3PIN_FSLS SUSPENDM _SERIAL 0 0 R/W/S/C R/W/S/C R/W/S 6PIN_FSLS _SERIAL 0 0 R/W/S/C © ...
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... Table 27 DRV_ CHRG_ VBUS VBUS R/W/S/C R/W/S/C Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver comparator. Either a digital FAULT is input on the /FAULT pin, not both. This bit BUS Section 9.5.2. DISCHRG_ DM_PULL DP_PULL VBUS DOWN DOWN ...
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... Table 29 shows the bit allocation of the register reserved R/W/S/C R/W/S/C Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver overcurrent indicator. BUS supply through the RESET_N/PSW_N pin. BUS . BUS . BUS . If DRV_VBUS_EXT is set to logic 1, BUS pulsing SRP. The link must ...
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... Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on Table 33) indicates the current value of the interrupt source signal reserved Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver SESS_ SESS_ VBUS_ END_F VALID_F VALID_F ...
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... Host Disconnect Latch: Automatically set when an unmasked event occurs on HOST_DISCON. Cleared when this register is read reserved Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver valid voltage comparator. BUS Table 35 SESS_ SESS_ VBUS_ END_L ...
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... The functionality of the PHY will not be affected. provides the bit allocation of the Power Control register reserved R/W/S/C R/W/S/C Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver BVALID_ BVALID_ reserved FALL RISE ...
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... Addresses 40h to FFh are not implemented. Operating on these addresses may result in undefined behavior of the PHY. ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 03 — 26 August 2008 © NXP B.V. 2008. All rights reserved ...
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... GND to achieve this 4 kV ESD protection (see BUS 1500 charge current discharge limit resistor resistance storage C S capacitor 100 pF Rev. 03 — 26 August 2008 ISP1505A; ISP1505C and GND) have a BUS Figure , see Section VBUS DEVICE UNDER TEST A B 0.1 F © NXP B.V. 2008. All rights reserved. 20). 16. ...
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... XTAL1 on pins DP and DM on pins DP, DM, V and GND; BUS I < all other pins; I < Conditions on pins STP, DATA[7:0] and RESET_N/PSW_N on pin V /FAULT BUS on pins DP and DM on pin XTAL1 . CC Rev. 03 — 26 August 2008 ISP1505A; ISP1505C Min Max 0.5 +4.6 0.5 +4.6 0 0.5 CC(I/O) 0.5 +6.0 0.5 +2.5 [1] 0.5 +4.6 [ ...
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... C; unless otherwise specified. CC(I/O) amb Conditions CC(I/ 0 CC(I/ 0 < V < CC(I/O) Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ 3.0 3.3 1.65 1.8 1 215 - [ [ [ [ ...
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... C; unless otherwise specified. CC(I/O) amb Conditions includes V range DI pull-up on pin pull-down on pins DP and DM GND L Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max 3.5 Min Typ Max ...
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... C to +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions for 1.5 k pull-up resistor includes V range DI pin to GND steady-state drive Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ 3.0 - 1425 1500 100 - 525 - 300 - ...
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... CHRG_VBUS is logic 1 connect to GND when DISCHRG_VBUS is logic +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. CC(I/O) amb Conditions SUSPENDM is logic 1 Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ Max 4.4 4.5 4.65 0.8 1.6 2.0 70 140 200 0 ...
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... STP Conditions 20 pF total external load per pin 20 pF total external load per pin Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Min Typ 0 ...
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... excluding the first transition from the idle state excluding the first transition from the idle state C = 200 pF to 600 pF; L 1.5 k pull-up on pin DM enabled Rev. 03 — 26 August 2008 ISP1505A; ISP1505C Min Typ Max - - 7 8.9 3.3 ...
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... DP RX_RCV, RX_DP and RX_DM; see Figure 24 DP RX_RCV, RX_DP and RX_DM; see Figure 24 DP RX_RCV, RX_DP and RX_DM; see Figure 24 DP RX_RCV, RX_DP and RX_DM; see Figure 24 Rev. 03 — 26 August 2008 ISP1505A; ISP1505C Min Typ Max 75 - 300 80 - 125 - - 11 ...
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... Fig 24. Timing of DP and DM to RX_RCV, RX_DP and CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 0 PLH(drv) differential V CRS data lines 2 CRS 0 PLH(rcv) ...
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... BUS 19.2 MHz 26 MHz - 100 pF Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Comment - - IP4359CX4/LF; Wafer-Level Chip-Scale Package (WLCSP); ESD IEC 61000-4-2 level contact air discharge compliant protection maximum value is determined by the voltage ...
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... STANDARD-A RECEPTACLE SHIELD 5 C VBUS A1 SHIELD 6 IP4359CX4/LF SHIELD B1 7 SHIELD 8 (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 26. Using the ISP1505 with a USB host controller; external 5 V source with built-in FAULT and external crystal V V CC(I/ bypass DATA1 1 DATA0 2 V CC(I/O) 3 ...
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... A1 A2 SHIELD 5 IP4359CX4/LF SHIELD ESD SHIELD 7 SHIELD C VBUS 8 f i(XTAL1) (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 27. Using the ISP1505 with a peripheral controller; external square wave input on pin XTAL1 V CC(I/ bypass DATA1 1 24 DATA0 CC(I/ RREF ...
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... 2.5 scale (1) ( 4.1 2.75 4.1 2.75 0.5 2.5 3.9 2.45 3.9 2.45 REFERENCES JEDEC JEITA MO-220 - - - Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION SOT616 ISSUE DATE ...
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... Solder bath specifications, including temperature and impurities ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 03 — 26 August 2008 © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 29. Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Figure 29) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... Identification International Electrotechnical Commission Low-Speed Magneto-Optical Non-Return-to-Zero Inverted On-The-Go Printed-Circuit Board Personal Digital Assistant Physical Layer Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver peak temperature © NXP B.V. 2008. All rights reserved. time 001aac844 ...
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... Transistor-Transistor Logic Transmit Command Universal Serial Bus USB Implementers Forum UTMI+ Low Pin Interface USB 2.0 Transceiver Macrocell Interface USB 2.0 Transceiver Macrocell Interface Plus Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver © NXP B.V. 2008. All rights reserved ...
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... Table 52 “Dynamic characteristics: digital I/O pins” Section 16 “Application information” Product data sheet on the DP and DM pins, and added Table note 1. I Product data sheet Rev. 03 — 26 August 2008 ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Change notice Supersedes - ISP1505A_ISP1505C_2 resume”: updated the resume” ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 26 August 2008 ISP1505A; ISP1505C © NXP B.V. 2008. All rights reserved ...
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... C = 0Fh) bit description . . . . . . . . . . . . . . . . . .48 Table 31. USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h, ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 48 Table 32. USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit description ...
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... XTAL1 . . . . . .64 Fig 28. Package outline SOT616-3 (HVQFN24 .65 Fig 29. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver Rev. 03 — 26 August 2008 © NXP B.V. 2008. All rights reserved ...
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... Modes of operation . . . . . . . . . . . . . . . . . . . . . 13 8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1.1 Synchronous mode 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 14 8.1.3 6-pin full-speed or low-speed serial mode . . . 15 ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 8.1.4 3-pin full-speed or low-speed serial mode . . . 15 8.2 USB and OTG state transitions . . . . . . . . . . . 16 9 Protocol description . . . . . . . . . . . . . . . . . . . . 18 9.1 ULPI references . . . . . . . . . . . . . . . . . . . . . . . 18 9.2 Power-On Reset (POR ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: ISP1505A_ISP1505C_3 All rights reserved. Date of release: 26 August 2008 ...