PIC18F2450 MICROCHIP [Microchip Technology], PIC18F2450 Datasheet - Page 237

• Manufacturer Part Number: PIC18F2450
• Description: 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

LFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
Decode
Q1
FSR2H
FSR2L
Read literal
Read literal
‘k’ MSB
‘k’ LSB
Load FSR
LFSR f, k
0
0
k
None
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
2
2
LFSR 2, 3ABh
Q2
1110
1111
=
=
f
k
FSRf
2
4095
03h
ABh
Process
Process
1110
0000
Data
Data
Q3
k
00ff
7
Write literal ‘k’
kkk
literal ‘k’ MSB
to FSRfH
to FSRfL
Advance Information
Write
Q4
k
kkkk
11
kkk
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
PIC18F2450/4450
Q1
register ‘f’
Move f
MOVF
0
d
a
f
N, Z
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
MOVF
Read
0101
Q2
=
=
=
=
f
[0,1]
[0,1]
dest
255
22h
FFh
22h
22h
f {,d {,a}}
REG, 0, 0
00da
Process
Data
Q3
DS39760A-page 235
95 (5Fh). See
ffff
Write W
Q4
ffff