PALCE20V8-10 CYPRESS [Cypress Semiconductor], PALCE20V8-10 Datasheet
PALCE20V8-10
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PALCE20V8-10 Summary of contents
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... It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. The PALCE20V8 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerdip, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and a 24-lead quarter size outline ...
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... GND Selection Guide Generic Part Number Com’l/Ind PALCE20V8−5 5 PALCE20V8−7 7.5 PALCE20V8−10 10 PALCE20V8−15 15 PALCE20V8−25 25 PALCE20V8L−15 15 PALCE20V8L−25 25 Shaded areas contain preliminary information. Document #: 38-03026 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS PLCC/LCC DIP/QSOP Top View 1 24 ...
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... Power-Up Reset All registers in the PALCE20V8 power- logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. Configuration Table ...
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... IH 15 Output Open MHz 15L, 25L ns (counter) 10, 15 15L, 25L ns Test Conditions MHz 2. MHz OUT Test Conditions Normal Programming Conditions PALCE20V8 [1] Ambient Temperature V CC ° ° 5V ± +75 C ° ° −40 5V ±10 +85 C ° ...
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... OL internal (1 measured (see Note 7 above) minus t MAX MAX3 FOR PALCE20V8 90% 10% ≤ TEST POINT Military R R Measured Output Value 390Ω 750Ω H ⎜ ⎜ 20V8−10 20V8−15 20V8−25 Min ...
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... Min. Max. [9] 1 [8] [8,10] [ [ 62.5 62.5 [8,13 [8, 14] [8] 1 FOR PALCE20V8 [3] 20V8−10 20V8−15 20V8−25 Min. Max. Min. Max. Min 45.5 37 62.5 62.5 41.6 62 20V8−15 20V8−25 Min. Max. ...
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... REGISTERED ACTIVE LOW OUTPUTS CLOCK Document #: 38-03026 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS 90 MAX = 1 µ PALCE20V8 [11] [11 PXZ ER EA PZX [11] [11 PXZ ER EA PZX Page ...
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... Functional Logic Diagram for PALCE20V8 PIN NUMBERS DIP (PLCC) PACKAGE 1 ( (3) 0 280 3 (4) 320 600 4 (5) 640 920 5 (6) 960 1240 6 (7) 1280 1560 7 (9) 1600 1880 8 (10) 1920 2200 9 (11) 2240 2520 10 (12) 11 (13) 2568 BYTE7 MSB LSB Document #: 38-03026 Rev ...
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... PALCE20V8−15LMB PALCE20V8−25JC PALCE20V8−25PC PALCE20V8−25QC 130 PALCE20V8−25JI PALCE20V8−25PI PALCE20V8−25QI PALCE20V8−25DMB PALCE20V8−25LMB Shaded areas contain preliminary information. Ordering Information for PALCE20V8L (mA) (ns) (ns) (ns) Ordering Code PALCE20V8L− ...
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... Ordering Information for PALCE20V8L (mA) (ns) (ns) (ns) Ordering Code PALCE20V8L−25JI PALCE20V8L−25PI PALCE20V8L−25QI PALCE20V8L−25DMB PALCE20V8L−25LMB Document #: 38-03026 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS (continued) Package Name J64 28-Lead Plastic Leaded Chip Carrier ...
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... Switching Characteristics Parameter Package Diagrams Document #: 38-03026 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS Subgroups Subgroups 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A PALCE20V8 51-80031-** Page ...
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... Package Diagrams (continued) Document #: 38-03026 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 PALCE20V8 51-85001-*A 51-80051-** Page ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000 TM FOR ALL NEW DESIGNS 24-Lead (300-Mil) PDIP P13 24-Lead Quarter Size Outline Q13 PALCE20V8 51-85013-*B 51-85055-B Page ...
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... Document History Page Document Title: PALCE20V8 Flash-Erasable Reprogrammable CMOS PAL Document Number: 38-03026 REV. ECN NO. Issue Date ** 106371 07/11/01 *A 122231 12/28/02 *B 213375 See ECN Document #: 38-03026 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS Orig. of Change SZV Changed from Spec Number: 38-00367 to 38-03026 RBI ...