PAL20V8 CYPRESS [Cypress Semiconductor], PAL20V8 Datasheet - Page 2

• Manufacturer Part Number: PAL20V8
• Description: Flash Erasable, Reprogrammable CMOS PAL Device
• Manufacturer: CYPRESS [Cypress Semiconductor]

Selection Guide
Shaded area contains preliminary information.
Functional Description
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
PALCE20V8 5
PALCE20V8 7
PALCE20V8 10
PALCE20V8 15
PALCE20V8 25
PALCE20V8L 15
PALCE20V8L 25
Pin Configuration
Generic Part Number
(continued)
Com’l/Ind
CLK/I
GND
I
10
I
I
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
7.5
10
15
25
15
25
0
5
DIP/QSOP
1
2
3
4
5
6
7
8
9
10
11
12
Top View
t
PD
ns
13
24
23
22
21
20
19
18
17
16
15
14
Mil
10
15
25
15
25
V
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OE/I
13
12
CC
7
6
5
4
3
2
1
0
11
20V8–2
Com’l/Ind
10
12
15
12
15
3
7
2
t
NC
S
I
I
I
I
I
I
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, V
Ground to improve noise immunity and reduce I
3
4
5
6
7
8
ns
5
6
7
8
9
10
11
Mil
10
12
20
12
20
121314 1516 1718
4 3 2
PLCC/LCC
Top View
1
Com’l/Ind
2827 26
10
12
10
12
4
5
7
25
24
23
22
21
20
19
t
CO
I/O
I/O
I/O
NC
I/O
I/O
I/O
ns
6
5
4
3
2
1
Mil
20V8–3
10
12
20
12
20
PALCE20V8
Com’l
115
115
115
90
90
55
55
I
CC
CC
mA
.
Mil/Ind
130
130
130
65
65
CC
, or