XC73144 XILINX [Xilinx, Inc], XC73144 Datasheet
XC73144
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XC73144 Summary of contents
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... Up to 167 MHz maximum clock frequency • Advanced Dual-Block architecture – Fast Function Blocks – High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144) • 100% interconnect matrix • High-speed arithmetic carry network – ripple-carry delay per bit – MHz 18-bit accumulators • ...
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XC7300 EPLD Family Output I/O Block Figure 1. XC7300 Device Block Diagram mize power dissipation. Designers can operate speed-criti- cal paths at maximum performance, while non-critical paths dissipate less power. Xilinx development software supports XC7300 EPLD design using third-party schematic ...
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... UIM 9 from FFB Macrocell 9 Feedback 5 Private P-Terms per Macrocell Feedback to UIM Pin Feedback to UIM Figure 2. Fast Function Block and Macrocell Schematic for the XC7318, XC7336, and XC73144 2 Global 2 Fast OE AND Array 12 from Fast 12 Input Pins 24 3 Inputs from UIM 9 from FFB ...
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... Each Fast Function Block output is capable of sinking 24 mA when volts. These include all outputs on CCIO the XC7318 and XC7336 devices and all Fast Outputs (FOs) on the XC7354, XC7372, XC73108, and XC73144 devices. Unlike other I/Os, the Fast Function Block inputs do not have an input register. Product Term Assignment ...
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AND Array 21 Inputs from UIM 3 from Fast Input Pins (FI) 12 Sharable 5 Private P-Terms per P-Terms per Function Block Macrocell More Macrocells Shift-In from Previous MC Shift-Out to Next ...
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Q output identical to the D input, independent of the clock conventional flip-flop. The Macrocell clock source is programmable and can be one of the private product terms or one of two global Fast- CLK ...
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... Block outputs can sink 24 mA when V puts on the XC7318 and XC7336 devices connect to FFBs. Outputs listed as Fast Outputs (FO) on the XC7354, XC7372, XC73108 and XC73144 devices con- nect to FFBs. Each signal input to the chip is connected to a program- mable input structure that can be configured as direct, latched, or registered. The latch and fl ...
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XC7300 EPLD can be exposed to without damage is 7000 W • s/cm 2 mately one week at 12,000 W/cm Design Recommendations For proper operation, all unused input and I/O pins must be connected to a ...
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XC7300 EPLD Family t FOE FOE t I, I/O IN Input Register t SUIN t HIN t CE SUCEIN t HCEIN t COIN FAST t IN INPUT FCLK Figure 8. XC7300 Timing Model Synchronous Clock Switching Characteristics F Pin CLK ...
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Combinatorial Switching Characteristics Input, I/O Pin UIM Delay Logic Delay P-Term Assignment Delay Transparent Register Delay Output Buffer Output Pin Asynchronous Clock Switching Characteristics Input, I/O Pin t IN Input, I/O Delay UIM Delay Clock at Register Data from Logic ...