MC68HC11E1 MOTOROLA [Motorola, Inc], MC68HC11E1 Datasheet - Page 31

• Manufacturer Part Number: MC68HC11E1
• Description: M68HC11E Series Programming Reference Guide
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Compare Force Register (CFORC)
Configuration Register (CONFIG)
MOTOROLA
Resets:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
Resets:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
Single chip:
Single chip:
Expanded:
Expanded:
Address:
FOC[1:5] — Force Output Comparison
Bits [2:0] — Unimplemented
Security disable, COP, ROM mapping, and EEPROM enables
The following register description applies to the MC68HC11E2 only.
Bootstrap:
Bootstrap:
Address:
Address:
Reset:
Read:
Write:
M68HC11E Series Programming Reference Guide
Write 1s to force compare(s).
Always read 0
Read:
Read:
Write:
Write:
Test:
Test:
0 = Not affected
1 = Output x action occurs
$100B
FOC1
Bit 7
$103F
$103F
0
Bit 7
Bit 7
EE3
U
U
0
0
0
0
1
1
= Unimplemented
= Unimplemented
= Unimplemented
FOC2
6
0
EE2
U
U
6
0
0
0
0
6
1
1
FOC3
5
0
EE1
U
U
5
0
0
0
0
5
1
1
FOC4
4
0
EE0
U
U
4
0
0
0
0
4
1
1
FOC5
NOSEC
NOSEC
3
0
U
U
U
U
3
1
1
3
1
1
NOCOP
NOCOP
2
0
U(L)
U(L)
U(L)
U(L)
M68HC11E Series Registers
U
U
U
U
2
2
ROMON
M68HC11ERG/AD
1
0
U
U
U
1
1
1
1
1
1
1
Bit 0
EEON
EEON
0
Bit 0
Bit 0
U
U
U
U
U
1
1
0
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