CY8C52 CYPRESS [Cypress Semiconductor], CY8C52 Datasheet - Page 43

• Manufacturer Part Number: CY8C52
• Description: Programmable System-on-Chip (PSoC)
• Manufacturer: CYPRESS [Cypress Semiconductor]

7.5.1 CAN Features
Document Number: 001-55034 Rev. *A
CAN2.0A/B protocol implementation - ISO 11898 compliant
Listen Only mode
SW readable error counter and indicator
Sleep mode: Wake the device from sleep with activity on the
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
Enhanced interrupt controller
Standard and extended frames with up to 8 bytes of data per
frame
Message filter capabilities
Remote Transmission Request (RTR) support
Programmable bit rate up to 1 Mbps
CAN receive and transmit buffers status
CAN controller error status including BusOff
CAN Node 1
PSoC
CAN_H
En
CAN Transceiver
CAN Controller
Drivers
CAN
Tx Rx
CAN_L
Figure 7-18. CAN Bus System Implementation
PRELIMINARY
CAN Node 2
CAN_H
CAN_L
7.5.2 Software Tools Support
CAN Controller configuration integrated into PSoC Creator:
Receive path
Transmit path
CAN Configuration walkthrough with bit timing analyzer
Receive filter setup
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that cov-
ers the ID, IDE and RTR
DeviceNet addressing support
Multiple receive buffers linkable to build a larger receive mes-
sage array
Automatic transmission request (RTR) response handler
Lost received message notification
Eight transmit buffers
Programmable transmit priority
Round robin
Fixed priority
Message transmissions abort capability
PSoC
CAN Bus
®
5: CY8C52 Family Data Sheet
CAN Node n
CAN_H
CAN_L
Page 43 of 85
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