CY8C38_11 CYPRESS [Cypress Semiconductor], CY8C38_11 Datasheet - Page 30

• Manufacturer Part Number: CY8C38_11
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Document Number: 001-11729 Rev. *R
Active
Alternate
Active
Sleep
Hibernate
Note
Power Modes
Active
Alternate
Active
Sleep
Hibernate <100 µs
13. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See
Active
Alternate Active
Sleep
Hibernate
Modes
Sleep
and
<15 µs
Wakeup
–
–
Table
Time
Primary mode of operation, all
peripherals available
(programmable)
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
6-3. The power modes allow a design to
200 nA
1.2 mA
–
1 µA
Description
Current
(typ)
[13]
Yes
User
defined
No
No
Execution
Code
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
Resources
All
All
I
None
2
C
Digital
Table 11-2
on page 65.
All
All
Comparator ILO/kHzECO
None
Resources
Any interrupt
Any interrupt
Comparator,
PICU, I
CTW, LVD
PICU
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins.
transitions between power modes
Analog
2
C, RTC,
All
None
Clock Sources
All
Figure 6-5
Available
Any
(programmable)
Any
(programmable)
ILO/kHzECO
Active Clocks
PSoC
on page 31 illustrates the allowable
Wakeup Sources
–
–
Comparator,
PICU, I
CTW, LVD
PICU
®
3: CY8C38 Family
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
2
C, RTC,
Data Sheet
Regulator
Page 30 of 129
All
All
XRES, LVD,
WDR
XRES
Sources
Reset
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