MC68HC05K1 FREESCALE [Freescale Semiconductor, Inc], MC68HC05K1 Datasheet - Page 67

• Manufacturer Part Number: MC68HC05K1
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

7.3.2 Data Direction Register A
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
NOTE:
Address:
The contents of data direction register A (DDRA), shown in
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the associated port A
pin; a logic 0 disables the output buffer. A reset initializes all DDRA bits
to logic 0s, configuring all port A pins as inputs. If the pulldown devices
are enabled by mask option, setting a DDRA bit to a logic 1 turns off the
pulldown device for that pin.
DDRA7–DDRA0 — Port A Data Direction Bits
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
Reset:
Read:
Write:
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
$0004
Bit 7
0
Figure 7-2. Data Direction Register A (DDRA)
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Parallel Input/Output (I/O)
DDRA6
6
0
DDRA5
5
0
DDRA4
4
0
DDRA3
3
0
DDRA2
Parallel Input/Output (I/O)
2
0
DDRA1
1
0
Technical Data
Figure
DDRA0
Bit 0
Port A
7-2,
0