A80960HA25SL2GX INTEL [Intel Corporation], A80960HA25SL2GX Datasheet - Page 16

• Manufacturer Part Number: A80960HA25SL2GX
• Description: 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
• Manufacturer: INTEL [Intel Corporation]

80960HA/HD/HT
10
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
BSTALL
XINT7:0
HOLDA
HOLD
BREQ
Name
BOFF
CT3:0
NMI
Type
R(Q)
H(Q)
H(Q)
B(Q)
B(Q)
S(L)
H(1)
B(0)
S(L)
R(0)
R(0)
H(Z)
B(Z)
R(Z)
A(E)
A(L)
A(E)
O
O
O
O
I
I
I
I
HOLD REQUEST signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:
Completes the current bus request.
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET pin is asserted.
HOLDA is never granted while LOCK is asserted.
BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
When BOFF is asserted, the address, data, and control buses are floated on the
next clock cycle and the current access is aborted.
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See
BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ can be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.
BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it can no longer execute strictly
out of on-chip cache memory).
CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs can be programmed to be level (low or high) or edge (rising or falling)
sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act
as the five most significant bits of a vectored source. The least significant bits of
the vectored source are set to “010” internally.
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
Cycle Type
Program-initiated access using 8-bit bus
Program-initiated access using 16-bit bus
Program-initiated access using 32-bit bus
Event-initiated access using 8-bit bus
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
Reserved for future products
Reserved
Figure 16 on page 40
for BOFF timing requirements.
Description
Advance Information
ADSCT3:0
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
Datasheet