MPC8533E_10 FREESCALE [Freescale Semiconductor, Inc], MPC8533E_10 Datasheet - Page 65

• Manufacturer Part Number: MPC8533E_10
• Description: Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8533E SerDes
reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).
For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock
input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Please
consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a
particular clock driver chip.
Figure 48
It assumes the DC levels of the clock driver are compatible with MPC8533E SerDes reference clock
input’s DC requirement.
Freescale Semiconductor
Single-Ended
CLK Driver Chip
Clock Driver
LVPECL CLK
Driver Chip
Clock Driver
Clock Driver
Figure 47. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
CLK_Out
CLK_Out
CLK_Out
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Figure 48. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω differential PWB trace
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
R2
R2
50
100 Ω differential PWB trace
Ω
10nF
10nF
10nF
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
50 Ω
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
50 Ω
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
MPC8533E
MPC8533E
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