NG80960JA-16 INTEL [Intel Corporation], NG80960JA-16 Datasheet - Page 69

• Manufacturer Part Number: NG80960JA-16
• Description: EMBEDDED 32-BIT MICROPROCESSOR
• Manufacturer: INTEL [Intel Corporation]

5.2
Table 25.
Advance Information Datasheet
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins.
Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
Boundary-Scan Register Bit Order
NOTE:
1. Enable cells are active low.
Bit
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
6
7
8
9
RDYRCV (TDI)
WIDTH/HLTD1
WIDTH/HLTD0
CONTROL1
CONTROL2
BLAST
Signal
XINT0
XINT1
XINT2
XINT3
XINT4
XINT5
XINT6
XINT7
HOLD
DT/R
FAIL
ADS
ALE
W/R
NMI
D/C
A2
A3
Enable cell
Enable cell
Output
Input/
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
1
1
Bit
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
LOCK/ONCE
LOCK/ONCE
HOLDA
BSTAT
Signal
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
DEN
ALE
BE0
BE1
BE2
BE3
cell
80960JA/JF/JD/JT 3.3 V Microprocessor
Enable cell
Output
Input/
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
1
Bit
49
48
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
AD cells
RESET
STEST
Signal
CLKIN
(TDO)
AD17
AD16
AD15
AD14
AD13
AD12
AD10
AD11
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Output
Enable
Input/
cell
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
1
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