PIC12F609-H/MD MICROCHIP [Microchip Technology], PIC12F609-H/MD Datasheet - Page 113

• Manufacturer Part Number: PIC12F609-H/MD
• Description: 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

12.3.5
On power-up, the time-out sequence is as follows:
• PWRT time-out is invoked after POR has expired.
• OST is activated after the PWRT time-out has
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F609/615/617/
12HV609/615 device operating in parallel.
Table 12-6 shows the Reset conditions for some
special registers, while Table 12-5 shows the Reset
conditions for all the registers.
TABLE 12-1:
TABLE 12-2:
TABLE 12-3:
 2010 Microchip Technology Inc.
XT, HS, LP
RC, EC, INTOSC
PCON
STATUS
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1:
Oscillator Configuration
Legend: u = unchanged, x = unknown
expired.
Name
POR
0
u
u
u
u
u
Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TIME-OUT SEQUENCE
Bit 7
IRP
BOR
—
x
0
u
u
u
u
TIME-OUT IN VARIOUS SITUATIONS
STATUS/PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 6
RP1
—
TO
1
1
0
0
u
1
T
PWRT
PWRTE = 0
Bit 5
RP0
PIC12F609/615/617/12HV609/615
—
T
T
PWRT
OSC
PD
+ 1024 •
1
1
u
0
u
0
Power-up
Bit 4
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
TO
—
PWRTE = 1
1024 • T
—
Bit 3
PD
—
OSC
12.3.6
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
Bit 0 is BOR (Brown-out). BOR is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOR = 0, indicating that
a Brown-out has occurred. The BOR Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BOREN<1:0> = 00 in the
Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent Reset, if POR is ‘0’, it will indicate that a Power-
on Reset has occurred (i.e., V
low).
For more information, see Section 12.3.4 “Brown-out
Reset (BOR)”.
Bit 2
—
T
Z
PWRT
PWRTE = 0
T
T
PWRT
OSC
+ 1024 •
Brown-out Reset
Bit 1
POR
DC
POWER CONTROL (PCON)
REGISTER
Condition
Bit 0
BOR
C
PWRTE = 1
1024 • T
—
---- --qq ---- --uu
0001 1xxx 000q quuu
POR, BOR
Value on
OSC
DD
may have gone too
DS41302D-page 113
Wake-up from
1024 • T
Sleep
Resets
Value on
all other
—
OSC
(1)