PIC12C672 MICROCHIP [Microchip Technology], PIC12C672 Datasheet - Page 36

• Manufacturer Part Number: PIC12C672
• Description: 8-Pin, 8-Bit CMOS Microcontroller with EEPROM Data Memory
• Manufacturer: MICROCHIP [Microchip Technology]

PIC12CE5XX
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
8.5
In the PIC12CE5XX, the DRT runs any time the device
is powered up. DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
V
stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high level. Thus,
programming GP3/MCLR/V
external RC network connected to the MCLR input is
not required in most cases, allowing for savings in
cost-sensitive and/or space restricted applications, as
well as allowing the use of the GP3/MCLR/V
a general purpose input.
The Device Reset time delay will vary from chip to chip
due to V
AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out (only in XT and LP modes). This is
particularly important for applications using the WDT
to wake from SLEEP mode automatically.
DS40172A-page 36
DD
INTERNAL RESET
to rise above V
INTERNAL POR
DRT TIME-OUT
Device Reset Timer (DRT)
DD
, temperature, and process variation. See
MCLR
V
DD
When V
this example, the chip will reset properly if, and only if, V1
DD
min., and for the oscillator to
DD
PP
rises slowly, the T
as MCLR and using an
DRT
T
PP
DRT
time-out expires long before V
pin as
V1
Preliminary
TABLE 8-5:
8.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The
programming the configuration bit WDTE as a '0'
(Section 8.1). Refer to the PIC12CE5XX Programming
Specifications to determine how to access the
configuration word.
IntRC &
ExtRC
XT & LP
Configuration
Oscillator
WDT
V
Watchdog Timer (WDT)
DD
DD
min.
has reached its final value. In
can
DRT (DEVICE RESET TIMER
PERIOD)
18 ms (typical)
18 ms (typical)
be
POR Reset
DD
): SLOW V
permanently
1997 Microchip Technology Inc.
DD
18 ms (typical)
Subsequent
RISE TIME
(typical)
Resets
disabled
300 s
by