CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 25

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

6.0
The CP3UB17 supports a uniform 16M-byte linear address
space. Table 8 lists the types of memory and peripherals
that occupy this memory space. Unlisted address ranges
6.1
The operating environment controls whether external mem-
ory is supported and whether the reset vector jumps to a
code space intended to support In-System Programming
(ISP). Up to 8M of external memory space is available.
The operating mode of the device is controlled by the states
on the ENV2:0 pins at reset, as shown in Table 9.
Internal pullups on the ENV2:0 pins select IRE mode or ISP
mode if these pins are allowed to float.
ENV2:0
0E EC00h
0E C000h
0E E800h
FF FB00h
FF FC00h
0E 0000h
0E 2000h
0E 8000h
0E 9200h
0E F000h
0E F140h
0E F180h
0E F200h
FF 0000h
00 0000h
04 0000h
10 0000h
40 0000h
80 0000h
Address
x10
111
011
000
Start
Table 9 Operating Environment Selection
Memory
OPERATING ENVIRONMENT
In-System-Programming (ISP) mode
Internal ROM enabled (IRE) or ISP mode
External ROM enabled (ERE) mode
Development (DEV) mode
0D FFFFh
0E BFFFh
0E EBFFh
0E EFFFh
FE FFFFh
FF FBFFh
0E 1FFFh
0E 7FFFh
0E E7FFh
0E F1FFh
0F FFFFh
3F FFFFh
7F FFFFh
FF FAFFh
FF FFFFh
03 FFFFh
0E 91FFh
0E F13Fh
0E F17Fh
Address
End
Operating Environment
Size in
3072K
4096K
8128K
Bytes
64256
11.5K
67.5K
256K
640K
4.5K
24K
10K
320
128
256
8K
1K
1K
1K
64
Table 8 CP3UB17 Memory Map
On-chip Flash Program Memory, including Boot
Memory
Reserved
On-chip Flash Data Memory
Reserved
Reserved
Reserved
System RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
External Memory Zone 1
External Memory Zone 2
BIU Peripherals
I/O Expansion
Peripherals and Other I/O Ports
25
are reserved and must not be read or written. The BIU
zones are regions of the address space that share the same
control bits in the Bus Interface Unit (BIU).
When ENV2:0 = 111, IRE mode is selected unless the
EMPTY bits in the Protection word indicate that the program
flash memory is empty (unprogrammed), in which case ISP
mode is selected. See Section 8.4.2 for more details. The
ENV2 pin is only available on the 100-pin packages, there-
fore it is not possible to enter the ERE or DEV environments
on the 48-pin versions of the CP3UB17.
In the DEV environment, the on-chip flash memory is dis-
abled, and the corresponding region of the address space
is mapped to external memory.
6.2
The BIU controls the interface between the CPU core bus
and those on-chip modules which are mapped into BIU
zones. These on-chip modules are the flash program mem-
ory and the I/O zone. The BIU controls the configured pa-
rameters for bus access (such as the number of wait states
for memory access) and issues the appropriate bus signals
for the requested access.
Description
BUS INTERFACE UNIT (BIU)
Static Zone 0
(mapped internally
in IRE and ERE
mode; mapped to
the external bus in
DEV mode)
N/A
Static Zone 1
Static Zone 2
I/O Zone
N/A
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BIU Zone