CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 105

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

PCMCONV The PCM to PCM Conversion Format bit se-
RESOLUTION The PCM Resolution field specifies the reso-
17.9.10 CVSD Status Register (CVSTAT)
The CVSTAT register is a 16-bit wide, read-only register that
holds the status information of the CVSD/PCM module. At
reset, and if the CVCTL1.CVEN bit is clear, all implemented
bits are cleared.
CVNE
CVNF
PCMINT
15
7
CVINST
lects the PCM format for PCM/PCM conver-
sions.
0 – Linear PCM <-> 8-bit µ-Law PCM
1 – Linear PCM <-> 8-bit A-Law PCM
lution of the PCM format for the linear PCM/
CVSD conversions. It also affects log data,
because log data is converted to 16-bit linear
form before resolution adjustment. After reset,
these two bits are clear.
00 – 16-bit linear PCM
01 – 15-bit linear PCM
10 – 14-bit linear PCM
11 – 13-bit linear PCM
Reserved
The CVSD In FIFO Nearly Empty bit indicates
when only three CVSD data words are left in
the CVSD In FIFO, so new CVSD data should
be written into the CVSD In FIFO. If the CVS-
DINT bit is set, an interrupt will be asserted
when the CVNE bit is set. If the DMACI bit is
set, a DMA request will be asserted when this
bit is set. The CVNE bit is cleared when the
CVSTAT register is read.
0 – CVSD In FIFO is not nearly empty.
1 – CVSD In FIFO is nearly empty.
The CVSD Out FIFO Nearly Full bit indicates
when only three empty word locations are left
in the CVSD Out FIFO, so the CVSD Out
FIFO should be read. If the CVSDINT bit is
set, an interrupt will be asserted when the
CVNF bit is set. If the DMACO bit is set, a
DMA request will be asserted when this bit is
set. The CVNF bit is cleared when the
CVSTAT register is read.
0 – CVSD Out FIFO is not nearly full.
1 – CVSD Out FIFO is nearly full.
The PCM Interrupt bit set indicates that the
PCMOUT register is full and needs to be read
or the PCMIN register is empty and needs to
be loaded with new PCM data. The PCMINT
bit is cleared when the CVSTAT register is
read.
0 – PCM does not require service.
1 – PCM requires loading or unloading.
5
CVF
4
CVE PCMINT CVNF CVNE
3
11
2
10
CVOUTST
1
0
8
105
CVE
CVF
CVINST
CVOUTST
The CVSD In FIFO Empty bit indicates when
the CVSD In FIFO has been read by the
CVSD converter while the FIFO was already
empty. If the CVSDERRORINT bit is set, an
interrupt will be asserted when the CVE bit is
set. The CVE bit is cleared when the CVSTAT
register is read.
0 – CVSD In FIFO has not been read while
1 – CVSD In FIFO has been read while emp-
The CVSD Out FIFO Full bit set indicates
whether the CVSD Out FIFO has been written
by the CVSD converter while the FIFO was al-
ready full. If the CVSDERRORINT bit is set,
an interrupt will be asserted when the CVF bit
is set. The CVF bit is cleared when the
CVSTAT register is read.
0 – CVSD Out FIFO has not been written
1 – CVSD Out FIFO has been written while
The CVSD In FIFO Status field reports the
current number of empty 16-bit word locations
in the CVSD In FIFO.
CVSD Out FIFO Status field reports the cur-
rent number of valid 16-bit CVSD data words
in the CVSD Out FIFO.
empty.
ty.
while full.
full.
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