KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 39

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Synchronous Interface
For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the
asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire
synchronous transfer.
The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type C)
burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a
VLBus-like or EISA-like burst transfer – if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the
interface is for EISA-like burst transfer.
Summary
Figure 12 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the switch’s BIU.
Figure 13 shows the connection for different data bus sizes.
For detail 8/16-bit bus signal connections and descriptions refers to Application Note 132.
For detail 32-bit bus signal connections and descriptions refers to Application Note 137.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so even
address will enable the BE0N and odd address will enable the BE1N.
Micrel, Inc.
October 2007
For VLBus-like transfer interface (VLBUSN = 0):
This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched
A [15:4] and qualifies with AEN (Address Enable) to determine if the switch is the intended target. No burst is
supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application
is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a
handshaking process to end the cycle of VLBus-like transfers. When the KSZ8842M is ready to finish the cycle, it
asserts SRDYN
the read data. The KSZ8842M holds the read data until RDYRTNN is asserted. The timing waveform is shown in
Figures 23 and 24.
For EISA-like burst transfer interface (VLBUSN = 1):
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to
indicate the burst write. Note that in this application, both the system/host/memory and KSZ8842M are capable of
inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8842M
to insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figures 21 and 22.
BE2N, BE1N, and BE0N are ignored as shown in the Figure 19. No other registers can be accessed by asserting
DATACSN. The data transfer is the same as in the first case. Independent of the type of asynchronous interface
used. To insert a wait state, the BIU will assert ARDY to prolong the cycle.
.
The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched
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KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9