ML67Q4002 OKI [OKI electronic componets], ML67Q4002 Datasheet - Page 17

• Manufacturer Part Number: ML67Q4002
• Description: 32-bit ARM-Based General-Purpose Microcontroller
• Manufacturer: OKI [OKI electronic componets]

External memory controller
Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM), IO
devices, and internal FLASH memory.
(1) ROM (FLASH) access function
(2) SRAM access function
(3) DRAM access function
made.
(4) External IO access function
Power Management
HALT, STANDBY, clock gear, clock control functions are supported as power save functions.
(1) HALT mode
(2) STANDBY mode
(3) Clock gear
(4) Clock control by each function unit
OKI Semiconductor
Supports 16-bit devices.
Supports FLASH memory:
In ML67Q4002/ML67Q4003, control internal FLASH access.
Configurable access timing.
Supports 16-bit devices.
Supports asynchronous SRAM
Configurable access timing.
Supports 16-bit device
Supports EDO/SDRAM
Configurable access timing.
Supports 8-bit/16-bit access
Each bank has two chip selects
Supports external wait input
Access Timing configurable for each bank independently
HALT object
HALT mode setting: Set by the system control register.
Exit HALT mode due to: Reset, interrupt
Stops the clock of entire LSI.
STANDBY mode setting: Specified by the system control register.
Exit
This LSI has two clock systems, HCLK and CCLK. Configure HCLK and CCLK frequency.
HCLK: CPU, bus control, synchronous serial interface, I2C.
CCLK: Timers, PWM, UART, AD converter, etc.
AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), UART, Synchronous SIO, I2C.
CPU, internal RAM, AHB bus control
STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)
Byte write (can be written only by IF equivalent to SRAM).
: 1 bank
: 1 bank
: 1 bank
: Simultaneous connections to EDO-DRAM and SDRAM cannot be
: 2 banks
: Independent configuration for each bank
: XIOCS_N[3:0]
: XWAIT
ML674001/67Q4002/67Q4003
FEDL674001-01
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