CY8C20180_09 CYPRESS [Cypress Semiconductor], CY8C20180_09 Datasheet - Page 15

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CY8C20180_09

Manufacturer Part Number
CY8C20180_09
Description
CapSense Express-8 Configurable IOs
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Document History Page
Document Number: 001-17346 Rev. *F
Document Title: CY8C20180 CapSense Express™ - 8 Configurable IOs
Document Number: 001-17346
Rev.
*A
*B
*C
*D
*E
*F
**
ECN No.
1341766
1494145
1773608
2091026
2404731
2544918
2648811
DZU/MOHD/
DZU/MOHD
DZU/PYRS
TUP/AESA
TUP/AESA
ZSK/AESA
TUP/FSU
Change
Orig. of
/AESA
PYRS
Submission
09/06/2008
See ECN
See ECN
See ECN
See ECN
See ECN
01/28/09
Date
New Data Sheet
Changed to FINAL Datasheet
Removed table - 2.7V DC General Purpose IO Specifications - Open Drain with
a pull up to 1.8V
Updated Logic Block Diagram
Removed table - 3V DC General Purpose IO Specifications
Updated Logic Block Diagram
Updated table - DC POR and LVD Specifications
Updated table - DC Chip Level Specifications
Updated table - 5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Updated table - AC GPIO Specifications and split it into two tables for 5V/3.3V
and 2.7V
Added section on CapSense Express
Updated 16-QFN Package Diagram
Updated table-DC Chip Level Specifications
Updated table-Pin Definitions 16 pin COL
Updated table-Pin Definitions 16 pin SOIC
Updated table-5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Changed definition for Timing for Fast/Standard Mode on the I2C Bus diagram
Updated Logic Block Diagram
Added DC Programming Specifications Table
Updated Features
Added CapSense Electrical Characteristics Table
Different sleep modes explained
Bi-Directional Sleep Control Pin defined
Table added on “2.7V DC Spec for I2C Line with 1.8V External Pull-Up
Included section on I2C Device Addressing
Updated CapSense Electrical Specifications table
Deleted VOH5, VOH6, VOH7, and VOH8 parameters
Description of Change
TM
Software tool
CY8C20180
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