XA3S1400A XILINX [Xilinx, Inc], XA3S1400A Datasheet - Page 17

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XA3S1400A

Manufacturer Part Number
XA3S1400A
Description
XA Spartan-3A Automotive FPGA Family Data Sheet
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
DS681 (v1.1) February 3, 2009
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
The numbers in this table are tested using the methodology presented in
Table 8
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
DCM output jitter is included in all measurements.
Symbol
ICKOFDCM
T
ICKOF
and
R
Table
When reading from the Output Flip-Flop
(OFF), the time from the active transition on
the Global Clock pin to data appearing at the
Output pin. The DCM is in use.
When reading from OFF, the time from the
active transition on the Global Clock pin to
data appearing at the Output pin. The DCM is
not in use.
11.
Table
22. If the latter is true, add the appropriate Output adjustment from
Description
www.xilinx.com
LVCMOS25
output drive, Fast slew
rate, with DCM
LVCMOS25
output drive, Fast slew
rate, without DCM
Conditions
Table 26
(2)
(2)
, 12mA
, 12mA
(3)
and are based on the operating conditions set forth in
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
Table
Device
25.
Speed Grade
Max
3.27
3.33
3.50
3.99
5.24
5.12
5.34
5.69
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
17

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