XC3042 XILINX [Xilinx, Inc], XC3042 Datasheet
XC3042
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XC3042 Summary of contents
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XC3000 Logic Cell Array Families Overview .............................................................. 2-104 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families ................................. 2-105 Architecture ...................................................... 2-106 Programmable Interconnect ............................. 2-111 Crystal Oscillator .............................................. 2-117 Programming ................................................... 2-118 Special Configuration Functions ...................... 2-122 Master Serial ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Overview Introduced in 1987/88, XC3000 is the industry’s most successful family of FPGAs, with over 10 million devices shipped. In 1992/93, Xilinx introduced three additional families, offering more speed, functionality, and ...
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... Excellent reliability record Device XC3020, 3020A, 3020L, 3120, 3120A XC3030, 3030A, 3030L, 3130, 3130A XC3042, 3042A, 3042L, 3142, 3142A XC3064, 3064A, 3064L, 3164, 3164A XC3090, 3090A, 3090L, 3190, 3190A XC3195, 3195A XC3000, XC3000A, XC3000L, XC3100, XC3100A ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families The XC3000 Logic Cell Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades. Architecture The perimeter of configurable IOBs provides a pro- grammable interface between ...
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Read or Write Data Figure 2. Static Configuration Memory Cell loaded with one bit of configuration program and controls one program selection in the Logic Cell Array. The memory cell outputs Q and Q use ground and V ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer threshold of the IOBs can be ...
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Configurable Logic Block The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. The XC3020 has 64 such blocks arranged in 8 ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Any Function Variables Any Function Variables ...
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RD which, when enabled and High, is dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops’ ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Figure 8. XACT Development System Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs ...
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Figure 9. LCA General-Purpose Interconnect. Composed of a grid of metal segments that may be intercon- nected through switch matrices to form networks for CLB and IOB inputs and outputs ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Figure 12. XC3020 Die-Edge IOBs. The XC3020 die-edge IOBs are provided with direct access to adjacent CLBs. 2-114 X2660 ...
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Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND func- tion. A logic High on both buffer inputs creates a high impedance, ...
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Each horizontal Longline is also driven by a weak keeper circuit that prevents undefined floating levels by maintaining the pre- vious logic level when the line is not driven by an active buffer ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Suggested Component Values R1 0.5 – – (may be required for low frequency, phase)t (shift and/or compensation level for crystal Q) C1 – ...
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... Clear Is ~ 200 Cycles for the XC3020—130 to 400 µs ~ 250 Cycles for the XC3030—165 to 500 µs ~ 290 Cycles for the XC3042—195 to 580 µs ~ 330 Cycles for the XC3064—220 to 660 µs ~ 375 Cycles for the XC3090—250 to 750 µs ...
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... Configuration Data Frames (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits Postamble Code (4 Bits Minimum) XC3020 XC3030 XC3042 XC3020A XC3030A XC3042A XC3020L XC3030L XC3042L XC3120 XC3130 XC3142 XC3120A XC3130A XC3142A 1,000 to 1,500 to 2,000 to 1,500 2,000 3,000 64 ...
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DIN Preamble Length Count The configuration data consists of a composite * 40-bit preamble/length count, followed by one or more concatenated LCA programs, separated by 4-bit postambles. An additional final postamble bit is added for each slave device and ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options in the MakeBits program allow timing choices of one clock ...
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IOB pull- up resistors in the Operational mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of a Logic ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Serial Mode * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 DURING CONFIGURATION THE PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ...
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Master Serial Mode Programming Switching Characteristics CCLK (Output) 1 Serial Data In Serial DOUT n – 3 (Output) Description CCLK Data In setup Data In hold Notes power-up, V must rise from 2 delayed ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Parallel Mode * * + Readback is Activated, a 5-kΩ Resistor is M0 M1PWRDWN Required in Series With M1 5 kΩ CCLK DOUT M2 HDC RCLK ...
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Master Parallel Mode Programming Switching Characteristics A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description RCLK To address valid To data setup To data hold RCLK High RCLK Low Notes power-up, V must rise from 2.0 V ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Peripheral Mode CONTROL ADDRESS SIGNALS BUS +5 V REPROGRAM Figure 23. Peripheral Mode. Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS ...
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Peripheral Mode Programming Switching Characteristics WRITE TO LCA WS, CS0, CS1 CS2 D0-D7 CCLK RDY/BUSY DOUT Description Write Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required DIN Hold time required RDY/BUSY delay after end ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Slave Serial Mode Micro Computer STRB D0 D1 I/O D2 Port RESET Figure 24. Slave Serial Mode. In Slave Serial mode, an external signal drives the ...
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Slave Serial Mode Programming Switching Characteristics DIN 1 T DCC CCLK DOUT (Output) Description CCLK To DOUT DIN setup DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit of CCLK Low time is caused by ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families General LCA Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description RESET (2) M0, M1, M2 setup time required M0, M1, ...
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Performance Device Performance The XC3000 families of FPGAs can achieve very high performance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. • Careful optimization of transistor ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 26. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 100 XC3100-3 ...
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... V connection. This condition can produce CC invalid power conditions and should be avoided. A large series resistor might be used to limit the current or a bipolar buffer may be used to isolate the input signal. 2-135 XC3042L XC3142A 0.07 0.25 mW per MHz 0.50 1.70 mW per MHz ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Descriptions Permanently Dedicated Pins Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on ...
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User I/O Pins that can have special functions. M2 During configuration, this input has a weak pull-up resistor. Together with M0 and M1 sampled before the start of configuration to establish the configuration mode to be used. After ...
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... I 148 E1 193 I 151 D1 199 I 152 C1 200 I/O 203 155 E3 I 156 C2 204 I/O All Others X X XC3020 etc XC3030 etc XC3042 etc. X XC3064 etc XC3090 etc XC3195 X5266 ...
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... Number of Available I/O Pins 44 64 Max I/O XC3020/XC3120 64 XC3030/XC3130 XC3042/XC3142 96 XC3064/XC3164 120 XC3090/XC3190 144 XC3195 176 Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package. In some cases, the chip has more pads than there are pins on the package, as indicated by the informa- tion (“ ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. XC3030 1 GND 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 PWRDWN 8 TCLKIN-I/O 9 I/O ...
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... This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118 pads on the XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads, indicated by an asterisk, do not exist on the XC3020, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020. Six pads on the XC3020 and 16 pads on the XC3030, indicated by a dash (— ...
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... I/O 52 I/O 53 XTL2(IN)-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed ouptuts are default slew-rate limited. In the PC84 package, XC3064, XC3090 and XC3195 have additional V XC3020/XC3030/XC3042. PLCC Pin Number XC3064, XC3090, XC3195 54 55 DONE- ...
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... This table describes the pinouts of three different chips in three different packges. The pin-description column lists 100 of the 118 pads on the XC3042 that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020, which has 74 pads ...
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... N14 A13 I/O* M13 C12 I/O L12 Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (14) for the XC3042. XC3042 XC3042 PGA Pin XC3064 XC3064 Number M1-RD P14 RESET ...
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... HDC-I/O 42 I/O 43 I/O 44 I/O 45 LDC-I/O 46 I/O* 47 I/O 48 I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (24) for the XC3042. XC3042 Pin XC3064 Number 49 I/O 50 I/O* 51 I/O 52 I/O 53 INIT-I/O 54 VCC 55 GND ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PQFP PQFP XC3064, XC3090, Pin Number XC3195 Pin Number * 1 I I ...
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XC3000 Families 175-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PGA Pin PGA Pin XC3090, XC3195 Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 C14 B3 I/O B15 C4 I/O D14 B4 ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number XC3090 1 PWRDWN 2 TCLKIN-I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O ...
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XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number Number XC3090 1 – 2 GND 3 PWRDWN 4 TCLKIN-I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Description PG223 PQ208 A9-I/O B1 206 A10-I/O E3 205 I/O E4 204 I/O C2 203 I/O C1 202 I/O D2 201 A8-I/O E2 200 A11-I/O F4 199 I/O F3 198 ...
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... XC3042A - XC3064A - XC3090A - XC3020L C XC3030L C C XC3042L C XC3064L C XC3090L XC3120A - ...
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed ...