XC4VFX12 XILINX [Xilinx, Inc], XC4VFX12 Datasheet - Page 3

• Manufacturer Part Number: XC4VFX12
• Manufacturer: XILINX [Xilinx, Inc]

SelectIO Technology
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ChipSync Technology
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System Blocks Specific to the FX Family
RocketIO Multi-Gigabit Transceiver (MGT)
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DS112 (v1.1) September 10, 2004
Advance Product Specification
Up to 960 user I/Os
Wide selections of I/O standards from 1.5V to 3.3V
Extremely high-performance
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True differential termination
Selected low-capacitance I/Os for improved signal
integrity
Same edge capture at input and output I/Os
Memory interface support for DDR and DDR-2
SDRAM, QDR-II, RLDRAM-II, and FCRAM-II
Integrated with SelectIO technology to simplify
source-synchronous interfaces
Per-bit deskew capability built in all I/O blocks (variable
input delay line)
Dedicated I/O and regional clocking resources (pin and
trees)
Built in data serializer/deserializer logic in all I/O and
clock dividers
Memory/Networking/Telecommunication interfaces up
to 1 Gb/s+
Full-duplex serial transceiver (MGT) capable of
622 Mb/s to 11.1 Gb/s baud rates
8b/10b, 64b/66b, user-defined FPGA logic, or no data
encoding
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable continuous time equalization for the
receiver
Programmable discrete feedback equalization for the
receiver
On-chip AC coupled receiver
Receiver signal detect and loss of signal indicator
Transmit driver sleep mode
User dynamic reconfiguration using secondary
configuration bus
600 Mb/s HSTL & SSTL (on all single-ended I/O)
1 Gb/s LVDS (on all differential I/O pairs)
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Digitally Controlled Impedance (DCI)
Active I/O Termination
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System Monitor
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A/D Converter Blocks
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Configuration
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90 nm Copper CMOS Process
1.2V Core Voltage
PowerPC 405 RISC Core
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Optional series or parallel termination
Temperature compensation
On-chip or off-chip temperature sensing capability
On-chip or off-chip voltage monitoring capability
Peak detect and alarm features
Supplemental A/D converter block in selected devices
10-bit / 200 kilo samples per second (kSPS or KHz)
Dedicated analog I/O pins
256-bit AES bitstream decryption provides intellectual
property (IP) security
Improved bitstream error detection/correction capability
Fast SelectMAP configuration
JTAG support
Readback capability
Embedded PowerPC 405 (PPC405) core
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Auxiliary Processor Unit (APU) Interface for direct
connection from PPC405 to coprocessors in fabric
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Up to 450 MHz operation
Five-stage data path pipeline
16 KB instruction cache
16 KB data cache
Enhanced instruction and data on-chip memory
(OCM) controllers
Additional frequency ratio options between
PPC405 and Processor Local Bus
APU can run at different clock rates
Supports autonomous instructions: no pipeline
stalls
32-bit instruction and 64-bit data
4-cycle cache line transfer
Virtex-4 Family Overview
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