XC4008 XILINX [Xilinx, Inc], XC4008 Datasheet - Page 33

• Manufacturer Part Number: XC4008
• Description: Logic Cell Array Families
• Manufacturer: XILINX [Xilinx, Inc]

CCLK
INIT
Notes:
Synchronous Peripheral Mode Programming Switching Characteristics
CCLK
RDY/BUSY
Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in
the first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on
every eighth consecutive rising edge of CCLK.
The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation
does not require such a response.
The pin name RDY/BUSY is a misnomer; in Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
Note that data starts to shift out serially on the DOUT pin 0.5 CLK periods after it was loaded in parallel. This obviously
requires additional CCLK pulses after the last byte has been loaded.
DOUT
INIT (High) Setup time required
D0-D7 Setup time required
D0-D7 Hold time required
CCLK High time
CCLK Low time
CCLK Frequency
Description
BYTE
0
0
1
2-39
1
2
3
Symbol
2
T
T
T
T
T
F
IC
DC
CD
CCH
CCL
CC
BYTE 0 OUT
3
4
Min
60
50
60
5
0
5
BYTE
1
6
Max
7
8
BYTE 1 OUT
0
Units
MHz
ns
ns
ns
ns
1
s
X6096