XCS05-3BG100C XILINX [Xilinx, Inc], XCS05-3BG100C Datasheet - Page 35

• Manufacturer Part Number: XCS05-3BG100C
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

DS060 (v1.6) September 19, 2001
Product Specification
SAMPLE PRELOAD
(* if PROGRAM = High)
SAMPLE/PRELOAD
Figure 30: Power-up Configuration Sequence
SAMPLE/PRELOAD
CONFIGURE*
CONFIGURE
Boundary Scan
READBACK
EXTEST*
BYPASS
Instructions
Available:
BYPASS
BYPASS
EXTEST
USER 1
USER 2
R
Master CCLK
Goes Active
Configuration Memory
F
If Boundary Scan
is Selected
Test MODE, Generate
One Time-Out Pulse
Completely Clear
Data to DOUT
Keep Clearing
Configuration
Configuration
Configuration
Count Equals
Yes
of 16 or 64 ms
Data Frame
Yes
Operational
Once More
Mode Line
Sequence
Load One
Yes
No
Start-Up
Memory
memory
High? if
Sample
Master
Config-
Length
Frame
uration
CCLK
Count
Valid
Error
Pass
V CC
INIT
Full
Yes
Yes
No
No
No
No
Master Delays Before
Sampling Mode Line
~1.3 s per Frame
Pull INIT Low
and Stop
PROGRAM
= Low
DS060_30_080400
Yes
Spartan and Spartan-XL Families Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL Express mode, the length count bits are ignored,
and DOUT is held Low, to disable the next device in the
pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error by
pulling the open-drain INIT pin Low. After all configuration
frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL Express mode, when the first device is fully pro-
grammed, DOUT goes High to enable the next device in the
chain.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the FPGA keeps clearing its configuration memory.
When PROGRAM goes High, the configuration memory is
cleared one more time, followed by the beginning of config-
uration, provided the INIT input is not externally held Low.
Note that a Low on the PROGRAM input automatically
forces a Low on the INIT output. The Spartan/XL PRO-
GRAM pin has a permanent weak pull-up. Avoid holding
PROGRAM Low for more than 500 s.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the FPGA
to wait after completing the configuration memory clear
operation. When INIT is no longer held Low externally, the
device determines its configuration mode by capturing the
state of the Mode pins, and is ready to start the configura-
tion process. A master device waits up to an additional
300 s to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Figure
30.)
35