XC3S1000-4CP132C XILINX [Xilinx, Inc], XC3S1000-4CP132C Datasheet - Page 60

• Manufacturer Part Number: XC3S1000-4CP132C
• Description: Spartan-3 FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
39
Notes:
1.
2.
3.
4.
Setup Times
Hold Times
The numbers in this table are tested using the methodology presented in
forth in
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
add the appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data
before the clock’s active edge.
DCM output jitter is included in all measurements.
Symbol
T
T
T
T
PHDCM
PSDCM
PSFD
PHFD
Table 5
R
When writing to the Input
Flip-Flop (IFF), the time
from the setup of data at the
Input pin to the active
transition at a Global Clock
pin. The DCM is in use. No
Input Delay is programmed.
When writing to IFF, the
time from the setup of data
at the Input pin to an active
transition at the Global
Clock pin. The DCM is not
in use. The Input Delay is
programmed.
When writing to IFF, the
time from the active
transition at the Global
Clock pin to the point when
data must be held at the
Input pin. The DCM is in
use. No Input Delay is
programmed.
When writing to IFF, the
time from the active
transition at the Global
Clock pin to the point when
data must be held at the
Input pin. The DCM is not in
use. The Input Delay is
programmed.
and
Table
Description
8.
LVCMOS25
IOBDELAY = NONE,
with DCM
LVCMOS25
IOBDELAY = IFD,
without DCM
LVCMOS25
IOBDELAY = NONE,
with DCM
LVCMOS25
IOBDELAY = IFD,
without DCM
Conditions
www.xilinx.com
(4)
(4)
(2)
(2)
(3)
(3)
,
,
,
,
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 21
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
and are based on the operating conditions set
Table
Table
17. If this is true of the data Input,
–0.45
–0.12
–0.12
–0.43
–0.45
–0.47
–0.54
–0.49
–0.98
–0.40
–0.27
–1.19
–1.43
–1.38
–1.82
–2.57
17. If this is true of the data Input,
2.37
2.13
2.15
2.58
2.55
2.59
2.67
2.52
3.00
2.63
2.50
3.50
3.78
3.78
4.44
5.26
Min
-5
Speed Grade
–0.40
–0.05
–0.05
–0.38
–0.40
–0.42
–0.49
–0.44
–0.93
–0.35
–0.22
–1.14
–1.38
–1.33
–1.77
–2.52
2.71
2.35
2.36
2.95
2.91
2.96
3.05
2.88
3.46
3.02
2.87
4.03
4.35
4.35
5.12
6.06
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13