ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 30

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ADMC326TR

Manufacturer Part Number
ADMC326TR
Description
28-Lead ROM-Based DSP Motor Controller
Manufacturer
AD [Analog Devices]
Datasheet
ADMC326
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
SPORT1 TRANSMIT OR IRQ1
SPORT1 RECEIVE OR IRQ0
INTERRUPT FORCE
0 = DISABLE
1 = ENABLE
(MASK)
SOFTWARE 1
SOFTWARE 0
15
0
SOFTWARE 1
0 = DISABLE
1 = ENABLE
TIMER
PERIPHERAL (OR IRQ2)
IRQ2
14
0
13
0
15
Figure 26. Configuration of Interrupt Control Registers
0
12
0
INTERRUPT NESTING
14
0
11
0
13
0
10
0
12
0
0
9
11
0
IMASK (R/W)
8
0
10
0
7
0
4
0
9
0
6
0
0
3
–30–
8
0
ICNTL
IFC
0
0
5
2
0
7
4
0
1
0
6
0
0
0
3
0
5
0
DSP REGISTER
2
0
IRQ0 SENSITIVITY
IRQ1 SENSITIVITY
IRQ2 SENSITIVITY
4
0
1
0
0
3
0
0
2
0
TIMER
SPORT1 RECEIVE
(OR IRQ0)
SPORT1 TRANSMIT
(OR IRQ1)
SOFTWARE 0
DSP REGISTER
1
0
0
0
0 = LEVEL
1 = EDGE
DSP REGISTER
TIMER
SPORT1 RECEIVE OR IRQ0
SPORT1 TRANSMIT OR IRQ1
SOFTWARE 0
SOFTWARE 1
IRQ2
INTERRUPT CLEAR
0 = DISABLE
1 = ENABLE
(MASK)
REV. A

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