ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 16

• Manufacturer Part Number: ADMC326TR
• Description: 28-Lead ROM-Based DSP Motor Controller
• Manufacturer: AD [Analog Devices]

ADMC326
16-BIT PWM TIMER
Parameter
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
Gate Drive Chop Frequency Range
Select
VAUX0
VAUX1
VAUX2
Calibration (V
The single slope technique has been adapted on the ADMC326
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Three of the
main inputs (V1, V2, and V3) are directly connected as high
impedance voltage inputs. The fourth channel has been con-
figured with a serially-connected 4-to-1 multiplexer. Table VI
shows the multiplexer input selection codes. One of these auxiliary
multiplexed channels is used to calibrate the ramp against the
internal voltage reference (V
Comparing each ADC input to a reference ramp voltage, and tim-
ing the comparison of the two signals, performs the conversion
process. The actual conversion point is the time point intersec-
tion of the input voltage and the ramp voltage (V
Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp volt-
age used to perform the conversion is generated by driving a
C
GND
EXTERNAL
CHARGING
CAP
ICONST
VAUX0
VAUX2
VAUX1
Table VI. ADC Auxiliary Channel Selection
V2
V3
V1
REF
V
)
C
Figure 11. ADC Overview
MUX
4 -1
Table V. Fundamental Characteristics of PWM Generation Unit of ADMC326
MODECTRL (1)
ADCMUX1
0
0
1
1
COMP
COMP
REF
CRST
COMP
COMP
).
ICONST_TRIM<2:0>
(CAP RESET)
)
V1L
V2L
V3L
VAUXL
BLOCK
REGISTERS
12-BIT
TIMER
ADC
V
ADC
REF
MODECTRL (0)
ADCMUX0
0
1
0
1
PWMSYNC (CONVST)
C
CLK MODECTRL<7>
) as shown in
ADC REGISTERS
ADC1
ADC2
ADC3
ADCAUX
MODECTRL<0..1>
–16–
fixed current into an off-chip capacitor, where the capacitor
voltage is
Following reset, V
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be
programmed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMC326 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over an approximately 20% cur-
rent range.
The ADC system consists of four comparators and a single timer,
which may be clocked at either the DSP rate or half the DSP
rate depending on the setting of the ADCCNT bit (Bit 7) of the
MODECTRL register. When this bit is cleared, the timers count
at a slower rate of CLKIN. When this bit is set, they count at
CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
and ADCAUX are the registers that capture the conversion times,
which are effectively the timer value when the associated com-
parator trips.
COMPARATOR
PWMSYNC
V
OUTPUT
VIL
Figure 12. Analog Input Block Operation
Min
0
150
0.05
0.02
C
= 0 at t = 0. This reset and the start of the
t
T
VIL
PWM
V
–T
Typ
16
100
50
100
0
100
C
CRST
V
= (I/C)
C
t
Max
100
100
12.5
5
V
T
CMAX
CRST
Unit
Bits
ns
ns
Hz
MHz
ns
ns
s
s
s
REV. A
t
V1