SAA7183AWP PHILIPS [NXP Semiconductors], SAA7183AWP Datasheet - Page 25

• Manufacturer Part Number: SAA7183AWP
• Description: Digital Video Encoder EURO-DENC2
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 24 Logic levels and function of SRCV1
Table 25 Subaddress 6C and 6D
Table 26 Subaddress 6D
Table 27 Subaddress 6E
Table 28 Logic levels and function of PHRES
1996 Oct 02
HTRIG
VTRIG
SBLBN
PHRES
FLC
DATA BYTE
DATA BYTE
DATA BYTE
Digital Video Encoder (EURO-DENC2)
PHRES1
SRCV11
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
LOGIC LEVEL
LOGIC LEVEL
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = tbf (tbf)
PHRES0
SRCV10
0
1
0
1
0
1
0
1
0
1
sets the vertical trigger phase related to signal on RCV1 input
vertical blanking is defined by programming of FAL and LAL; default after reset
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
selects the phase reset mode of the colour subcarrier generator; see Table 28
field length control; see Table 29
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines or SECAM-specific if bit SECAM = 1
reset every eight fields
reset every four fields
not applicable
AS OUTPUT
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
FSEQ
VS
FS
not applicable
AS INPUT
FSEQ
VS
FS
25
DESCRIPTION
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field
(PAL = 0), eighth field (PAL = 1) or twelfth field
(SECAM = 1)
DESCRIPTION
DESCRIPTION
FUNCTION
SAA7182A; SAA7183A
FUNCTION
Preliminary specification