SAA7127 PHILIPS [NXP Semiconductors], SAA7127 Datasheet - Page 19

• Manufacturer Part Number: SAA7127
• Description: Digital video encoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 27 Subaddress 6BH
Table 28 Logic levels and function of SRCV1
Table 29 Subaddresses 6CH and 6DH
1999 May 31
PRCV2
ORCV2
CBLF
PRCV1
ORCV1
TRCV2
SRCV1
HTRIG
DATA BYTE
SRCV11
Digital video encoder
0
0
1
1
DATA BYTE
DATA BYTE
SRCV10
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset
polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
pin RCV2 is switched to input; default after reset
pin RCV2 is switched to output
If ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset.
If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset.
If ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL. If ORCV2 = LOW and bit SYMP = LOW, the signal input
to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking
signal.
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after
reset
polarity of RCV1 as output is active LOW, falling edge is taken when input
pin RCV1 is switched to input; default after reset
pin RCV1 is switched to output
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
defines signal type on pin RCV1; see Table 28
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
not applicable
AS OUTPUT
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG
decreases delays of all internally generated timing signals; reference mark: analog output
horizontal sync (leading slope) coincides with active edge of RCV used for triggering at
HTRIG = 39H
FSEQ
VS
FS
not applicable
AS INPUT
FSEQ
VS
FS
19
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)
DESCRIPTION
DESCRIPTION
SAA7126H; SAA7127H
FUNCTION
Product specification