ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 28

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
Table 29. AC Signal Specifications
Name
ADDR31–0
DATA63–0
MSH
MSSD3–0
MS1–0
RD
WRL
WRH
ACK
SDCKE
RAS
CAS
SDWE
LDQM
HDQM
SDA10
HBR
HBG
BOFF
BUSLOCK
BRST
BR7–0
BM
IORD
IOWR
IOEN
CPA
DPA
BMS
FLAG3–0
RST_IN
TMS
TDI
TDO
TRST
EMU
ID2–0
CONTROLIMP1–0
(All values in this table are in nanoseconds.)
7
3, 4
8
3, 4
2
8
Description
External Address Bus
External Data Bus
Memory Select HOST Line
Memory Select SDRAM Lines
Memory Select for Static Blocks
Memory Read
Write Low Word
Write High Word
Acknowledge for Data High to Low
Acknowledge for Data Low to High
SDRAM Clock Enable
Row Address Select
Column Address Select
SDRAM Write Enable
Low Word SDRAM Data Mask
High Word SDRAM Data Mask
SDRAM ADDR10
Host Bus Request
Host Bus Grant
Back Off Request
Bus Lock
Burst Pin
Multiprocessing Bus Request Pins
Bus Master Debug Aid Only
I/O Read Pin
I/O Write Pin
I/O Enable Pin
Core Priority Access High to Low
Core Priority Access Low to High
DMA Priority Access High to Low
DMA Priority Access Low to High
Boot Memory Select
FLAG Pins
Global Reset Pin
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Data Output (JTAG)
Test Reset (JTAG)
Emulation High to Low
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Rev. C | Page 28 of 48 | December 2006
1.5
1.5
—
1.5
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
—
—
—
1.5
1.5
1.5
—
1.5
1.5
—
—
—
—
1.5
1.5
1.5
1.5
—
—
1.5
1.5
1.5
—
1.5
—
—
—
0.5
0.5
—
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
0.5
0.5
0.5
—
0.5
0.5
—
—
—
—
0.5
0.5
0.5
0.5
—
—
2.5
0.5
0.5
—
0.5
—
—
—
4.0
4.0
4.0
4.0
4.0
4.0
3.6
4.2
4.0
4.0
4.0
4.0
4.0
4.0
—
4.0
—
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
29.5
4.0
29.5
4.0
—
—
—
4.0
—
5.5
—
—
4.0
4.0
4.0
4.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
0.9
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
1.0
—
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
1.0
2.0
1.0
1.0
—
—
—
1.0
—
2.0
—
—
1.15
1.15
1.15
1.0
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
—
1.15
—
1.15
1.15
—
—
1.0
1.15
1.15
0.75
0.75
0.75
0.75
1.15
1.15
—
—
—
0.75
—
1.15
—
—
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
—
2.0
—
2.0
2.0
—
—
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
—
—
—
2.0
—
4.0
—
—
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
TCK
TCK
TCK
TCK
TCK or SCLK
—
—
6
5